View STM32F756ZG_8543603.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

this is information on a product in full production. february 2016 docid027589 rev 4 1/228 stm32f756xx arm ? -based cortex ? -m7 32b mcu+fpu, 462dmips, up to 1mb flash/320+16+ 4kb ram, crypto, usb otg hs/fs, ethernet, 18 tims, 3 adcs, 25 com itf, cam & lcd datasheet - production data features ? core: arm ? 32-bit cortex ? -m7 cpu with fpu, adaptive real-time accelerator (art accelerator?) and l1-cache: 4kb data cache and 4kb instruction ca che, allowing 0-wait state execution from embedded flash memory and external memories, frequency up to 216 mhz, mpu, 462 dmips/2.14 dmips/mhz (dhrystone 2.1), and dsp instructions. ? memories ? up to 1mb of flash memory ? 1024 bytes of otp memory ? sram: 320kb (including 64kb of data tcm ram for critical real-time data) + 16kb of instruction tcm ram (for critical real-time routines) + 4kb of backup sram (available in the lowest power modes) ? flexible external memory controller with up to 32-bit data bus: sram, psram, sdram/lpsdr sdram, nor/nand memories ? dual mode quad-spi ? lcd parallel interface, 8080/6800 modes ? lcd-tft controller up to xga resolution with dedicated chrom-art accelerator? for enhanced graphic content creation (dma2d) ? clock, reset and supply management ? 1.7 v to 3.6 v application supply and i/os ? por, pdr, pvd and bor ? dedicated usb power ? 4-to-26 mhz crystal oscillator ? internal 16 mhz factory-trimmed rc (1% accuracy) ? 32 khz oscillator for rtc with calibration ? internal 32 khz rc with calibration ? low-power ? sleep, stop and standby modes ?v bat supply for rtc, 3232 bit backup registers + 4kb backup sram ? 312-bit, 2.4 msps adc: up to 24 channels and 7.2 msps in trip le interleaved mode ? 212-bit d/a converters ? up to 18 timers: up to thirteen 16-bit (1x low- power 16-bit timer available in stop mode) and two 32-bit timers, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input. all 15 timers running up to 216 mhz. 2x watchdogs, systick timer ? general-purpose dma: 16-stream dma controller with fifos and burst support ? debug mode ? swd & jtag interfaces ?cortex ? -m7 trace macrocell? ? up to 168 i/o ports with interrupt capability ? up to 164 fast i/os up to 108 mhz ? up to 166 5 v-tolerant i/os ? up to 25 communica tion interfaces ? up to 4 i 2 c interfaces (smbus/pmbus) ? up to 4 usarts/4 uarts (27 mbit/s, iso7816 interface, lin, irda, modem control) ? up to 6 spis (up to 50 mbit/s), 3 with muxed simplex i 2 s for audio class accuracy via internal audio pll or external clock ? 2 x sais (serial audio interface) ? 2 cans (2.0b active) and sdmmc interface ? spdifrx interface ? hdmi-cec ? advanced connectivity ? usb 2.0 full-speed device/host/otg controller with on-chip phy ? usb 2.0 high-speed/full-speed device/host/otg controller with dedicated dma, on-chip full-speed phy and ulpi ? 10/100 ethernet mac with dedicated dma: supports ieee 1588v2 hardware, mii/rmii ? 8- to 14-bit parallel camera interface up to 54 mbyte/s ? cryptographic acceleration: hardware acceleration for aes 128, 192, 256, triple des, hash (md5, sha-1, sha-2), and hmac ? true random number generator ? crc calculation unit ? rtc: subsecond accuracy, hardware calendar ? 96-bit unique id table 1. device summary reference part number stm32f756xx stm32f756vg, STM32F756ZG, stm32f756ig, stm32f756bg, stm32f756ng lqfp100 (14x14 mm) lqfp144 (20x20 mm) lqfp176 (24x24 mm) ufbga176 (10x10 mm) &"'! tfbga216 (13x13 mm) lqfp208 (28x28 mm) wlcsp143 (4.5x5.8 mm) tfbga100 (8x8 mm) www.st.com
contents stm32f756xx 2/228 docid027589 rev 4 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 arm ? cortex ? -m7 with fpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 18 2.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 axi-ahb bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 dma controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 flexible memory controller (fmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.9 quad-spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.10 lcd-tft controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.11 chrom-art accelerator? (dma2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 22 2.13 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.14 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.15 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.16 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.17 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.17.1 internal reset on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.17.2 internal reset off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.18 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.18.1 regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.18.2 regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.18.3 regulator on/off and inte rnal reset on/off availability . . . . . . . . . . 30 2.19 real-time clock (rtc), backup sram and backup registers . . . . . . . . . . 30 2.20 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.21 v bat operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.22 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.22.1 advanced-control timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid027589 rev 4 3/228 stm32f756xx contents 5 2.22.2 general-purpose timers (timx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.22.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.4 low-power timer (lptim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.5 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.6 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.22.7 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.23 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.24 universal synchronous/asynchronous re ceiver transmitters (usart) . . 37 2.25 serial peripheral interface (spi)/inter- integrated sound interfaces (i2s) . 38 2.26 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.27 spdifrx receiver interface (spdifrx) . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.28 audio pll (plli2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.29 audio and lcd pll(pllsai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.30 sd/sdio/mmc card host interface (sdmmc) . . . . . . . . . . . . . . . . . . . . . 40 2.31 ethernet mac interface with dedi cated dma and ieee 1588 support . . . 40 2.32 controller area network (bxcan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.33 universal serial bus on-the-go full-speed (otg_fs) . . . . . . . . . . . . . . . . 41 2.34 universal serial bus on-the-go high-speed (otg_hs) . . . . . . . . . . . . . . . 41 2.35 high-definition multimedia interface (hdmi) - consumer electronics control (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.36 digital camera interface (dcmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.37 cryptographic acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.38 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.39 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.40 analog-to-digital converters (adcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.41 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.42 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.43 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.44 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
contents stm32f756xx 4/228 docid027589 rev 4 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.2 vcap1/vcap2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.3.3 operating conditions at power-up / power-down (regulator on) . . . . . 102 5.3.4 operating conditions at power-up / power-down (regulator off) . . . . 102 5.3.5 reset and power control block characteristics . . . . . . . . . . . . . . . . . . 102 5.3.6 over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.7 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.8 wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.3.9 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.3.10 internal clock source char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.3.11 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.12 pll spread spectrum clock generatio n (sscg) characteristics . . . . . 132 5.3.13 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.14 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.3.15 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 138 5.3.16 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 5.3.17 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 5.3.18 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 5.3.19 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.20 rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.21 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 5.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.24 reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 5.3.25 dac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 5.3.26 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 5.3.27 fmc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
docid027589 rev 4 5/228 stm32f756xx contents 5 5.3.28 quad-spi interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 5.3.29 camera interface (dcmi) timing specifications . . . . . . . . . . . . . . . . . . 192 5.3.30 lcd-tft controller (ltdc) characteristics . . . . . . . . . . . . . . . . . . . . . 193 5.3.31 sd/sdio mmc card host interface (sdmmc) characteristics . . . . . . . 195 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 6.1 lqfp100, 14 x 14 mm low-profile quad flat package information . . . . . 197 6.2 tfbga100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6.3 wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 6.4 lqfp144, 20 x 20 mm low-profile quad flat package information . . . . . 206 6.5 lqfp176, 24 x 24 mm low-profile quad flat package information . . . . . 209 6.6 lqfp208, 28 x 28 mm low-profile quad flat package information . . . . . 213 6.7 ufbga 176+25, 10 x 10 x 0.65 mm ultra thin-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 6.8 tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 6.9 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 appendix a recommendations when using inte rnal reset off . . . . . . . . . . . 225 a.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
list of tables stm32f756xx 6/228 docid027589 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f756xx features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27 table 4. regulator on/off and internal reset on/off availability. . . . . . . . . . . . . . . . . . . . . . . . . 30 table 5. voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 8. usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 9. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 10. stm32f756xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 11. fmc pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 12. stm32f756xx alternate function ma pping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 13. stm32f756xx register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 14. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 15. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 16. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 17. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 18. limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 101 table 19. vcap1/vcap2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 20. operating conditions at power-up / power-down (r egulator on) . . . . . . . . . . . . . . . . . . . 102 table 21. operating conditions at power-up / power-down (r egulator off). . . . . . . . . . . . . . . . . . . 102 table 22. reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 23. over-drive switching characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 24. typical and maximum current consumption in run mode, code with data processing running from itcm ram, regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 25. typical and maximum current consumption in run mode, code with data processing running from flash memory (art on except prefetch / l1-cache on) or sram on axi (l1-cache on), regulator on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 26. typical and maximum current consumption in run mode, code with data processing running from flash memory or sram on axi (l1-cache disabled), regulator on . . . . . 107 table 27. typical and maximum current consumption in run mode, code with data processing running from flash memory on itcm interface (art disabled), regulator on . . . . . . . . 108 table 28. typical and maximum current consumption in run mode, code with data processing running from flash memory (art on except prefetch / l1-cache on) or sram on axi (l1-cache on), regulator off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 29. typical and maximum current consumption in sleep mode, regulator on. . . . . . . . . . . . 110 table 30. typical and maximum current consumption in sleep mode, regulator of f . . . . . . . . . . . 110 table 31. typical and maximum current consumptions in st op mode . . . . . . . . . . . . . . . . . . . . . . . 111 table 32. typical and maximum current consumptions in standby mode . . . . . . . . . . . . . . . . . . . . 112 table 33. typical and maximum current consumptions in v bat mode. . . . . . . . . . . . . . . . . . . . . . . 113 table 34. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 35. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 36. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 37. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 38. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 39. hse 4-26 mhz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 40. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 41. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
docid027589 rev 4 7/228 stm32f756xx list of tables 8 table 42. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 43. main pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 44. plli2s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 45. pllisai characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 46. sscg parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 47. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 48. flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 49. flash memory programming with vpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 50. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 51. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 52. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 53. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 table 54. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 55. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 56. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 57. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 58. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 table 59. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 table 60. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 61. rtc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 62. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 63. adc static accuracy at f adc = 18 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 64. adc static accuracy at f adc = 30 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 65. adc static accuracy at f adc = 36 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 66. adc dynamic accuracy at f adc = 18 mhz - limited test conditions . . . . . . . . . . . . . . . . . 149 table 67. adc dynamic accuracy at f adc = 36 mhz - limited test conditions . . . . . . . . . . . . . . . . . 149 table 68. temperature sensor characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 table 69. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 70. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 71. internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 table 72. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 73. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 74. minimum i2cclk frequency in a ll i2c modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 75. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 76. spi dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 77. i 2 s dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 78. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 79. usb otg full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 64 table 80. usb otg full speed dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 81. usb otg full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 82. usb hs dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 table 83. usb hs clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 table 84. dynamic characteristics: usb ulpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 85. dynamics characteristics: ethe rnet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . 168 table 86. dynamics characteristics: ethe rnet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . 168 table 87. dynamics characteristics: ethe rnet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 88. asynchronous non-multiplexed sram/psram/nor read timings . . . . . . . . . . . . . . . . . 172 table 89. asynchronous non-multiplexed sram/psram /nor read - nwait timings . . . . . . . . . . 172 table 90. asynchronous non-multiplexed sram/psram/nor write timings . . . . . . . . . . . . . . . . . 173 table 91. asynchronous non-multiplexed sram/psram/n or write - nwait timings. . . . . . . . . . 174 table 92. asynchronous multiplexed psram/nor read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 93. asynchronous multiplexed psram/nor read-nwai t timings . . . . . . . . . . . . . . . . . . . . 175
list of tables stm32f756xx 8/228 docid027589 rev 4 table 94. asynchronous multiplexed psram/nor write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 95. asynchronous multiplexed psram/nor write-nwai t timings . . . . . . . . . . . . . . . . . . . . 177 table 96. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 97. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 98. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 182 table 99. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 100. switching characteristics for nand flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 101. switching characteristics for nand flash write cycl es. . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 102. sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 103. lpsdr sdram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 88 table 104. sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 105. lpsdr sdram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 106. quad-spi characteristics in sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 107. quad-spi characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 108. dcmi characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 109. ltdc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 table 110. dynamic characteristics: sd / mmc characteristics, vdd=2.7v to 3.6v . . . . . . . . . . . . . 196 table 111. dynamic characteristics: e mmc characteristics, vdd=1.71v to 1.9v . . . . . . . . . . . . . . . 196 table 112. lqpf100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 198 table 113. tfbga100, 8 x 8 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 table 114. tfbga100 recommended pcb design rules (0.8 mm pitch bga). . . . . . . . . . . . . . . . . . 202 table 115. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 116. wlcsp143 recommended pcb design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 117. lqfp144, 20 x 20 mm, 144- pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 118. lqfp176, 24 x 24 mm, 176- pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 table 119. lqfp208, 28 x 28 mm, 208- pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 120. ufbga 176+25, 10 10 0.65 mm ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 table 121. ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) . . . . . . . . . . . . . 218 table 122. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 123. tfbga216 recommended pcb design rules (0.8 mm pitch bga). . . . . . . . . . . . . . . . . . 221 table 124. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 125. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 126. limitations depending on the operating power su pply range . . . . . . . . . . . . . . . . . . . . . . 225 table 127. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
docid027589 rev 4 9/228 stm32f756xx list of figures 11 list of figures figure 1. compatible board design for lqfp100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 2. stm32f756xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. stm32f756xx axi-ahb bus matrix architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4. vddusb connected to vdd power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. vddusb connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. power supply supervisor interconnection with in ternal reset off . . . . . . . . . . . . . . . . . . . 25 figure 7. pdr_on control with internal re set off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. startup in re gulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. stm32f756vx lqfp100 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 figure 12. stm32f756vx tfbga100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13. stm32f756zx wlcsp143 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 14. stm32f756zx lqfp144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 figure 15. stm32f756ix lqfp176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 16. stm32f756bx lqfp208 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 figure 17. stm32f756ix ufbga176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 18. stm32f756nx tfbga216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 19. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 20. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 21. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 22. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 23. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 24. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 25. typical v bat current consumption (rtc on/bkp sram off and lse in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 26. typical v bat current consumption (rtc on/bkp sram off and lse in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 27. typical v bat current consumption (rtc on/bkp sram off and lse in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 28. typical v bat current consumption (rtc on/bkp sram off and lse in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 29. typical v bat current consumption (rtc on/bkp sram off and lse in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 30. high-speed external clock source ac timing diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 31. low-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 32. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 figure 33. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 figure 34. hsi deviation versus temperatur e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 35. lsi deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 36. pll output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 figure 37. pll output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 38. ft i/o input ch aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 39. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 40. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 figure 41. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
list of figures stm32f756xx 10/228 docid027589 rev 4 figure 42. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 43. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 151 figure 44. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . 151 figure 45. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 46. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 47. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 48. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 59 figure 49. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 50. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 51. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 52. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 53. usb otg full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 165 figure 54. ulpi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 figure 55. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 56. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 57. ethernet mii timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 58. asynchronous non-multip lexed sram/psram/nor read waveforms . . . . . . . . . . . . . . 171 figure 59. asynchronous non-multip lexed sram/psram/nor write wavefo rms . . . . . . . . . . . . . . 173 figure 60. asynchronous multiplexed psram/nor read wavefo rms. . . . . . . . . . . . . . . . . . . . . . . . 174 figure 61. asynchronous multiplexed psram/nor write wave forms . . . . . . . . . . . . . . . . . . . . . . . 176 figure 62. synchronous multiplexed nor/ psram read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 figure 63. synchronous multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 figure 64. synchronous non-multiplexed nor/psram read ti mings . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 65. synchronous non-multiplexed psram write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 66. nand controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 67. nand controller waveforms for wr ite access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 figure 68. nand controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 185 figure 69. nand controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 186 figure 70. sdram read access waveforms (c l = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 figure 71. sdram write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 figure 72. quad-spi timing diagram - sdr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 73. quad-spi timing diagram - ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 74. dcmi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 75. lcd-tft horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 94 figure 76. lcd-tft vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 figure 77. sdio high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 78. sd default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 79. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 197 figure 80. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 81. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 figure 82. tfbga100, 8 8 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 figure 83. tfbga100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 84. tfbga100, 8 8 0.8mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 figure 85. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 figure 86. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
docid027589 rev 4 11/228 stm32f756xx list of figures 11 figure 87. wlcsp143, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 88. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 206 figure 89. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 figure 90. lqfp144, 20 x 20mm, 144-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 figure 91. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 209 figure 92. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 93. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 94. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 213 figure 95. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 96. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 figure 97. ufbga 176+25, 10 10 0.65 mm ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 figure 98. ufbga176+25, 10 x 10 x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 figure 99. ufbga 176+25, 10 10 0.6 mm ultra thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 100. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 101. tfbga216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 figure 102. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
description stm32f756xx 12/228 docid027589 rev 4 1 description the stm32f756xx devices are based on the high-performance arm ? cortex ? -m7 32-bit risc core operating at up to 216 mhz frequency. the cortex ? -m7 core features a single floating point unit (sfpu) pr ecision which supports all arm ? single-precision data- processing instructions and data types. it also implements a full set of dsp instructions and a memory protection unit (mpu) which enhances the application security. the stm32f756xx devices incorporate high-speed embedded memories with a flash memory up to 1 mbyte, 320 kbytes of sram (including 64 kbytes of data tcm ram for critical real-time data), 16 kbytes of instruction tcm ram (for critical real-time routines), 4 kbytes of backup sram available in the lowe st power modes, and an extensive range of enhanced i/os and peripherals connected to tw o apb buses, two ahb buses, a 32-bit multi- ahb bus matrix and a multi layer axi interconnect supporting internal and external memories access. all the devices offer three 12-bit adcs, two dacs, a low-power rtc, thirteen general- purpose 16-bit timers including two pwm timers for motor control and one low-power timer available in stop mode, two general-purpose 32-bit timers, a true random number generator (rng), and a cryptographic ac celeration cell. they also feature standard and advanced communication interfaces. ? up to four i 2 cs ? six spis, three i 2 ss in duplex mode. to achieve the audio class accuracy, the i 2 s peripherals can be clocked via a dedicated internal audio pll or via an external clock to allow synchronization. ? four usarts plus four uarts ? an usb otg full-spee d and a usb otg high- speed with full-speed capability (with the ulpi), ? two cans ? two sai serial audio interfaces ? an sdmmc host interface ? ethernet and camera interfaces ? lcd-tft display controller ? chrom-art accelerator? ? spdifrx interface ? hdmi-cec advanced peripherals include an sdmmc inte rface, a flexible memory control (fmc) interface, a quad-spi flash memory interface, a camera interface for cmos sensors and a cryptographic accelera tion cell. refer to table 2: stm32f756xx features and peripheral counts for the list of peripherals available on each part number. the stm32f756xx devices operate in the ?40 to +105 c temperature range from a 1.7 to 3.6 v power supply. a dedicated supply input for usb (otg_fs and otg_hs) is available on all the packages except lqfp100 for a greater power supply choice. the supply voltage can drop to 1.7 v with the use of an external power supply supervisor (refer to section 2.17.2: internal reset off ). a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f756xx devices offer devices in 8 packages ranging from 100 pins to 216 pins. the set of included peripherals changes with the device chosen.
docid027589 rev 4 13/228 stm32f756xx description 45 these features make the stm32f756xx microc ontrollers suitable for a wide range of applications: ? motor drive and application control, ? medical equipment, ? industrial applications: plc, inverters, circuit breakers, ? printers, and scanners, ? alarm systems, video intercom, and hvac, ? home audio appliances, ? mobile applications, internet of things, ? wearable devices: smartwatches. figure 2 shows the general block diagram of the device family. table 2. stm32f756xx features and peripheral counts peripherals stm32f756vx stm32f756zx stm32f756ix stm32f756bx stm32f756nx flash memory in kbytes 512 1024 512 1024 512 1024 512 1024 512 1024 sram in kbytes system 320(240+16+64) instruction 16 backup 4 fmc memory controller yes (1) ethernet yes timers general-purpose 10 advanced- control 2 basic 2 low-power 1 random number generator yes communication interfaces spi / i 2 s 4/3 (simplex) (2) 6/3 (simplex) (2) i 2 c4 usart/uart 4/4 usb otg fs yes usb otg hs yes can 2 sai 2 spdifrx 4 inputs sdmmc yes camera interface yes lcd-tft yes chrom-art accelerator? (dma2d) yes cryptography yes gpios 82 114 140 168 12-bit adc number of channels 3 16 24
description stm32f756xx 14/228 docid027589 rev 4 12-bit dac number of channels yes 2 maximum cpu frequency 216 mhz (3) operating voltage 1.7 to 3.6 v (4) operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216 1. for the lqfp100 package, only fmc bank1 is available. bank1 ca n only support a multiplexed nor/psram memory using the ne1 chi p select. 2. the spi1, spi2 and spi3 interfaces give the flexibility to work in an exclusive way in either the spi mode or the i2s audio m ode. 3. 216 mhz maximum frequency for -40c to + 85c ambient temperature range (200 mhz maximum frequency for -40c to + 105c ambie nt temperature range). 4. v dd /v dda minimum value of 1.7 v is obtained when the internal reset is off (refer to section 2.17.2: internal reset off ). table 2. stm32f756xx features and peripheral counts (continued) peripherals stm32f756vx stm32f756zx stm32f756ix stm32f756bx stm32f756nx
docid027589 rev 4 15/228 stm32f756xx description 45 1.1 full compatibility throughout the family the stm32f756xx devices are fu lly pin-to-pin, compatible wi th the stm32f4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. figure 1 give compatible board design s between the stm32f4xx families. figure 1. compatible board design for lqfp100 package the stm32f756xx lqfp144, lqfp176, lqfp208, tfbga216, ufbga176, wlcsp143 packages are fully pin to pin comp atible with stm32f4xxxx devices. 06y9 3& 9'' 966$ 95() 9''$ 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3& 3% 3% 9&$3 9'' 3( 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 670)[[670)[[ 670)[[ 966 9'' 966 3$ 3$ 3$ 3$ 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3& 3% 3% 9&$3 9'' 3( 3& 966$ 95() 9''$ 3lqvwrduhqrwfrpsdwleoh 3$:.83 3$ 3$ 3$ 3$:.83 3$ 3$
description stm32f756xx 16/228 docid027589 rev 4 figure 2. stm32f756xx block diagram 1. the timers connected to apb2 are clocke d from timxclk up to 216 mhz, while the timers connected to apb1 are clocked from timxclk either up to 108 mhz or 216 mhz depending on timpre bit configuration in the rcc_dckcfgr register. 069 'w/kwkzd ,lw? yd/dxt<hw ?& w??w? d/dlwtd e}u?oxzvx~d/dz,?we?eu ezvx~d/dz,?we?dzu </e?& h^zd zyudyuu^u^d?& /??l^dh^ ?z?v?d l dl &/&k d//}?zd//?& d/k?& h^ kd',^ wud h>w/w??w?u^><?w?u^e?w?u ^etue> et/du/edz ze' u? ]v??( ,^zeus^ze wh/y>??l, de ' d zd z ,^ z >^ ^?v? ]v??( /t' ?s th z??? o}l }v??}o w>>u?u? w>^ d/de d/d? ?zvvo??& o zvvo? &>^,d d/d d/d d/d? d/d? d/de d/d? d/d? &/&k w?ed,~u? ^zd?< ,??d, dl &/&k d 6wuhdpv ),)2 w??w? w??w? w??w? w??w? w&??w? w'??w? w,??w? w/??w? 'w/kwkzd 'w/kwkzd 'w/kwkzd 'w/kwkzd 'w/kwkzd& 'w/kwkzd' 'w/kwkzd, 'w/kwkzd/ d/d?lwtd d/d d/d ?u? ]? h^zd e}u?oxzvx~d/d?z,?we?eu ezvx~d/d?z,?we?udzu </e?& zvvo?& zvvo?& zyudyuu^u^d?& ^>u^u^d?& ^w/?l/?^? dk^/l^u^^ k^z/e k^zkhd ,>k^ er?d, &/&k ^w/e ^rd&d ),)2 ,zkdrzd ~d? w:??w? 'w/kwkzd: w<?& &/&k ez^ue^ues d^u^?? ,^, &/&k &/&k >zz?w?u>z'?w?u>z?w?u >z,^zeu>zs^zeu>zu >z>< zdz& zdz& zdz?, zd }???rd y/d ,w ,^ dd /dd dz< dz??w? :dz^du:d/u :d< :dkl^tu:dk :d'?^t es/ dd dwh ddzde< /ddzd< yr^w/ >wd/d ,d/z?& ,d/r ^w/&zy ^w/&zy??w??& ^>u^u^d?& /?el^dh^ ^/? ^u^<?& &/&k ???vouu}??}v??}oo?~&d ^zdu^zduw^zduekz&o?zu ee&o?z ?d, /rz e< rz e< ,?y/ ?s ?s ?s ?sd ]p]?o(]o?? ?s ?s dk^/l^u^ docid027589 rev 4 17/228 stm32f756xx functional overview 45 2 functional overview 2.1 arm ? cortex ? -m7 with fpu the arm ? cortex ? -m7 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and a low-power consumption, while delivering an outstanding computational performance and low interrupt latency. the cortex ? -m7 processor is a highly efficient high-performance featuring: ? six-stage dual-issue pipeline ? dynamic branch prediction ? harvard caches (4 kbytes of i-cache and 4 kbytes of d-cache) ? 64-bit axi4 interface ? 64-bit itcm interface ? 2x32-bit dtcm interfaces the processor supports the following memory interfaces: ? tightly coupled memory (tcm) interface. ? harvard instruction and data caches and axi master (axim) interface. ? dedicated low-latency ahb-lite peripheral (ahbp) interface. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu (float ing point unit) speeds up the software development by using metalanguage development tools, while avoiding saturation. figure 2 shows the general block diagram of the stm32f756xx family. note: cortex ? -m7 with fpu core is binary compatible with the cortex ? -m4 core. 2.2 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it.
functional overview stm32f756xx 18/228 docid027589 rev 4 2.3 embedded flash memory the stm32f756xx devices embed a flash memory of up to 1 mbyte available for storing programs and data. 2.4 crc (cyclic redundancy check) calculation unit the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify the data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a mean of verifying the flash memory integrity. the crc calculation unit helps to compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.5 embedded sram all the devices features: ? system sram up to 320 kbytes: ? sram1 on ahb bus matrix: 240 kbytes ? sram2 on ahb bus matrix: 16 kbytes ? dtcm-ram on tcm interface (tighly coupl ed memory interface): 64 kbytes for critical real-time data. ? instruction ram (itcm-ram) 16 kbytes: ? it is mapped on tcm interface and rese rved only for cpu execution/instruction useful for critical real-time routines. the data tcm ram is accessible by the gp-d mas and peripherals dmas through specific ahb slave of the cpu.the tcm ram instruction is reserved only for cpu. it is accessed at cpu clock speed with 0-wait states. ? 4 kbytes of backup sram this area is accessible only from the cpu. its content is protected against possible unwanted write accesses, and is retained in standby or v bat mode. 2.6 axi-ahb bus matrix the stm32f756xx system architectu re is based on 2 sub-systems: ? an axi to multi ahb bridge converting axi4 protocol to ahb-lite protocol: ? 3x axi to 32-bit ahb bridges connected to ahb bus matrix ? 1x axi to 64-bit ahb bridge connected to the embedded flash ? a multi-ahb bus-matrix: ? the 32-bit multi-ahb bu s matrix interconnects all the masters (cpu, dmas, ethernet, usb hs, lcd-tft, and dma2d) and the slaves (flash memory, ram, fmc, quad-spi, ahb and apb peripherals) and ensures a seamless and an efficient operation even when se veral high-speed peripherals work simultaneously.
docid027589 rev 4 19/228 stm32f756xx functional overview 45 figure 3. stm32f756xx axi-ahb bus matrix architecture 1. the above figure has large wires for 64- bits bus and thin wires for 32-bits bus. 2.7 dma controller (dma) the devices feature two general-purpose dual-port dmas (dma1 and dma2) with 8 streams each. they are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripher al transfers. they fe ature dedicated fifos for apb/ahb peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (ahb/apb). the two dma controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. the two dma controllers also have a double buffering feature, which autom ates the use and switching of two memory buffers without requiring any special code. 069 zd}???rd ??r]??d??]?r^ zd &>^, d ^zd ?e< ^zd? < , ??]?z? &d???vo du?o yr^w/ ,w y/?} uo?]r, , w?]?z ddzd /ddzd dd /dd y/d < e< er]?, er]?^d??]? /dd w w? ,^ ,'&dfkh .% 'w d 'w d? d ?z?v? h^kd' ,^ dzw/ dzdd dzdd? dzw? d,zedzd h^z,^zd >rd&d z?}urzd >rd&dzd d? o??}? ~d?
functional overview stm32f756xx 20/228 docid027589 rev 4 each stream is connected to dedicated hardware dma requests, with support for software trigger on each stream. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: ? spi and i 2 s ? i 2 c ? usart ? general-purpose, basic and advanced-control timers timx ? dac ? sdmmc ? cryptographic acceleration ? camera interface (dcmi) ? adc ? sai ? spdifrx ? quad-spi ? hdmi-cec 2.8 flexible memory controller (fmc) the flexible memory controller (fmc) includes three memory controllers: ? the nor/psram memory controller ? the nand/memory controller ? the synchronous dram (sdram/m obile lpsdr sdram) controller the main features of the fmc controller are the following: ? interface with static-memory mapped devices including: ? static random access memory (sram) ? nor flash memory/onenand flash memory ? psram (4 memory banks) ? nand flash memory with ecc hardware to check up to 8 kbytes of data ? interface with synchronous dram (sdr am/mobile lpsdr sdram) memories ? 8-,16-,32-bit data bus width ? independent chip select control for each memory bank ? independent configuration for each memory bank ? write fifo ? read fifo for sdram controller ? the maximum fmc_clk/fmc_sdclk frequen cy for synchronous accesses is hclk/2. lcd parallel interface the fmc can be configured to interface seamlessly with most graphic lcd controllers. it supports the intel 8080 and motorola 6800 modes, and is flexible enough to adapt to
docid027589 rev 4 21/228 stm32f756xx functional overview 45 specific lcd interfaces. this lcd parallel inte rface capability makes it easy to build cost- effective graphic applications using lcd modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.9 quad-spi memory interface (quadspi) all devices embed a quad-spi memory interf ace, which is a specialized communication interface targetting single, dual or quad-spi flash memories. it can work in: ? direct mode through registers. ? external flash status register polling mode. ? memory mapped mode. up to 256 mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access. code execution is supported. the opcode and the frame format are fully pr ogrammable. communication can be either in single data rate or dual data rate. 2.10 lcd-tft controller the lcd-tft display controller provides a 24-b it parallel digital rgb (red, green, blue) and delivers all signals to interface directly to a broad range of lcd and tft panels up to xga (1024x768) resolution with the following features: ? 2 displays layers with dedicated fifo (64x32-bit) ? color look-up table (clut) up to 256 colors (256x24-bit) per layer ? up to 8 input color formats selectable per layer ? flexible blending between two layers us ing alpha value (per pixel or constant) ? flexible programmable parameters for each layer ? color keying (transparency color) ? up to 4 programmable interrupt events. 2.11 chrom-art accelerator? (dma2d) the chrom-art accelerator? (dma2d) is a graphic accelerator which offers advanced bit blitting, row data copy and pixel format conv ersion. it supports the following functions: ? rectangle filling with a fixed color ? rectangle copy ? rectangle copy with pixel format conversion ? rectangle composition with blending and pixel format conversion. various image format coding are supported, from indirect 4bpp color mode up to 32bpp direct color. it embeds dedicated memory to store color lookup tables. an interrupt can be generated when an operation is complete or at a programmed watermark. all the operations are fully automatized and are running independently from the cpu or the dmas.
functional overview stm32f756xx 22/228 docid027589 rev 4 2.12 nested vectored inter rupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 97 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m7 with fpu core. ? closely coupled nvic gives low-latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving, higher-priority interrupts ? support tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimum interrupt latency. 2.13 external interrupt/ event controller (exti) the external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 clock period. up to 168 gpios can be connected to the 16 external interrupt lines. 2.14 clocks and startup on reset the 16 mhz internal hsi rc oscillator is selected as the default cpu clock. the 16 mhz internal rc oscillator is factory-trimmed to offer 1% accuracy. the application can then select as system clock either the rc osc illator or an external 4-26 mhz clock source. this clock can be monitored for failure. if a fa ilure is detected, the system automatically switches back to the inte rnal rc oscillator and a software in terrupt is genera ted (if enabled). this clock source is input to a pll thus allowing to increase the frequency up to 216 mhz. similarly, full interrupt management of the pll clock entry is available when necessary (for example if an indirectly us ed external oscillator fails). several prescalers allow t he configuration of the two ahb buses, the high-speed apb (apb2) and the low-sp eed apb (apb1) domains. the maxi mum frequency of the two ahb buses is 216 mhz while the maximum frequency of the high-speed apb domains is 108 mhz. the maximum allowe d frequency of the low-speed apb domain is 54 mhz. the devices embed two dedicated pll (plli2s and pllsai) which allow to achieve audio class performance. in this case, the i 2 s and sai master clock can generate all standard sampling frequencies from 8 khz to 192 khz.
docid027589 rev 4 23/228 stm32f756xx functional overview 45 2.15 boot modes at startup, the boot memory space is sele cted by the boot pin and boot_addx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3fff ffff which includes: ? all flash address space mapped on itcm or axim interface ? all ram address space: itcm, dtcm rams and srams mapped on axim interface ? the system memory bootloader the boot loader is located in system memory. it is used to reprogram the flash memory through a serial interface. 2.16 power supply schemes ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. ? v dd = 1.7 to 3.6 vexternal power supply for i/os and the internal regulator (when enabled), provided externally through v dd pins. ? v ssa , v dda = 1.7 to 3.6 v: external analog power supplies for adc, dac, reset blocks, rcs and pll. v dda and v ssa must be connected to v dd and v ss , respectively. note: v dd /v dda minimum value of 1.7 v is obtained when the internal reset is off (refer to section 2.17.2: internal reset off ). refer to table 3: voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. ? v ddusb can be connected either to v dd or an external independent power supply (3.0 to 3.6v) for usb transceivers (refer to figure 4 and figure 5 ). for example, when device is powered at 1.8v, an independent power supply 3.3v can be connected to v ddusb . when the v ddusb is connected to a separated power supply, it is independent from v dd or v dda but it must be the last supply to be provided and the first to disappear. the follo wing conditions v ddusb must be respected: ? during power-on phase (v dd < v dd_min ), v ddusb should be always lower than v dd ? during power-down phase (v dd < v dd_min ), v ddusb should be always lower than v dd ?v ddsub rising and falling time rate specif ications must be respected (see table 20 and table 21 ) ? in operating mode phase, v ddusb could be lower or higher than v dd: - if usb (usb otg_hs/otg_fs) is used, the associated gpios powered by v ddusb are operating between v ddusb_min and v ddusb_max . - the v ddusb supply both usb transceiver (u sb otg_hs and usb otg_fs). if only one usb transceiver is used in the ap plication, the gpios associated to the other usb transceiver are still supplied by v ddusb . - if usb (usb otg_hs/otg_fs) is not used, the associated gpios powered by v ddusb are operating between v dd_min and v dd_max .
functional overview stm32f756xx 24/228 docid027589 rev 4 figure 4. v ddusb connected to v dd power supply figure 5. v ddusb connected to external power supply 2.17 power supply supervisor 2.17.1 internal reset on on packages embedding the pdr_on pin, th e power supply supervisor is enabled by holding pdr_on high. on the other packa ges, the power supply supervisor is always enabled. the device has an integrated power-on reset (por)/ power-down reset (pdr) circuitry coupled with a brownout reset (bor) circuitry. at power-on, por/pdr is always active and ensures proper operation starting from 1.8 v. after the 1.8 v por threshold level is 9 ''b0,1 wlph 9 '' 9 ''$ 9 ''86% 3rzhurq 3rzhugrzq 2shudwlqjprgh 9 ''b0$; 9'' 069 069 9 ''86%b0,1 9 ''b0,1 wlph 9 ''86%b0$; 86% ixqfwlrqdoduhd 9 '' 9 ''$ 86%qrq ixqfwlrqdo duhd 9 ''86% 3rzhurq 3rzhugrzq 2shudwlqjprgh 86%qrq ixqfwlrqdo duhd
docid027589 rev 4 25/228 stm32f756xx functional overview 45 reached, the option byte loading process star ts, either to confirm or modify default bor thresholds, or to disable bor permanently. three bor thresholds are available through option bytes. the device remains in reset mode when v dd is below a specified threshold, v por/pdr or v bor , without the need for an external reset circuit. the device also features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 2.17.2 internal reset off this feature is available only on packages featuring the pdr_on pin. the internal power-on reset (por) / power-down reset (pdr) circui try is disabled through the pdr_on pin. an external power supply supervisor should monitor v dd and should maintain the device in reset mode as long as v dd is below a specified threshold. pdr_on should be connected to v ss . refer to figure 6: power supply supervisor interconnection with internal reset off . figure 6. power supply supervisor interconnection with internal reset off the v dd specified threshold, below which the device must be maintained under reset, is 1.7 v (see figure 7 ). a comprehensive set of power-saving mode allows to design low-power applications. when the internal reset is off, the following integrated features are no more supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled ? the brownout reset (bor) circuitry must be disabled ? the embedded programmable voltage detector (pvd) is disabled ? v bat functionality is no more available and v bat pin should be connected to v dd . all the packages, except for t he lqfp100, allow to disable the internal reset through the pdr_on signal when connected to v ss . 3'5b21 3'5qrwdfwlyhy9 '' y 9 %$7 $ssolfdwlrquhvhw vljqdorswlrqdo 06y9 9 '' 9 66
functional overview stm32f756xx 26/228 docid027589 rev 4 figure 7. pdr_on control with internal reset off 2.18 voltage regulator the regulator has four operating modes: ? regulator on ? main regulator mode (mr) ? low-power regulator (lpr) ? power-down ? regulator off 2.18.1 regulator on on packages embedding the bypass_reg pin, the regulator is enabled by holding bypass_reg low. on all ot her packages, the regula tor is always enabled. there are three power modes configured by software when the regulator is on: ? mr mode used in run/sleep modes or in stop modes ? in run/sleep mode the mr mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). different voltages scaling are provided to reach the best compromise between the maximum frequency and dynamic power 069 9 '' wlph 3'5 9 wlph 1567 3'5b21 3'5b21 5hvhwe\rwkhuvrxufhwkdq srzhuvxsso\vxshuylvru
docid027589 rev 4 27/228 stm32f756xx functional overview 45 consumption. the over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. ? in stop modes the mr can be configured in two ways during stop mode: mr operates in normal mode (default mode of mr in stop mode) mr operates in under-drive mode (reduced leakage mode). ? lpr is used in the stop modes: the lp regulator mode is configured by software when entering stop mode. like the mr mode, the lpr can be configured in two ways during stop mode: ? lpr operates in normal mode (default mode when lpr is on) ? lpr operates in under-drive mode (reduced leakage mode). ? power-down is used in standby mode. the power-down mode is activated only when entering in standby mode. the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. the contents of th e registers and sram are lost. refer to table 3 for a summary of voltage regulator modes versus device operating modes. two external ceramic capacitors should be connected on v cap_1 and v cap_2 pin. all packages have the regulator on feature. 2.18.2 regulator off this feature is availa ble only on packages fe aturing the bypass_reg pi n. the regulator is disabled by holding bypass_reg high. the regulator off mode allows to supply externally a v 12 voltage source through v cap_1 and v cap_2 pins. since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.the two 2.2 f ceramic capacitors should be replaced by two 100 nf decoupling capacitors. when the regulator is off, there is no more internal monitoring on v 12 . an external power supply supervisor should be used to monitor the v 12 of the logic power domain. pa0 pin should be used for this purpose, and act as power-on reset on v 12 power domain. table 3. voltage regulator configuration mode versus device operating mode (1) 1. ?-? means that the corresponding configuration is not available. voltage regulator configuration run mode sleep mode stop mode standby mode normal mode mr mr mr or lpr - over-drive mode (2) 2. the over-drive mode is not available when v dd = 1.7 to 2.1 v. mr mr - - under-drive mode - - mr or lpr - power-down mode - - - yes
functional overview stm32f756xx 28/228 docid027589 rev 4 in regulator off mode, the following features are no more supported: ? pa0 cannot be used as a gpio pin sinc e it allows to reset a part of the v 12 logic power domain which is not reset by the nrst pin. ? as long as pa0 is kept low, the debug mode cannot be used under power-on reset. as a consequence, pa0 and nrst pins must be managed separately if the debug connection under reset or pre-reset is required. ? the over-drive and under-drive modes are not available. ? the standby mode is not available. figure 8. regulator off the following conditions must be respected: ? v dd should always be higher than v cap_1 and v cap_2 to avoid current injection between power domains. ? if the time for v cap_1 and v cap_2 to reach v 12 minimum value is faster than the time for v dd to reach 1.7 v, then pa0 should be k ept low to cover both conditions: until v cap_1 and v cap_2 reach v 12 minimum value and until v dd reaches 1.7 v (see figure 9 ). ? otherwise, if the time for v cap_1 and v cap_2 to reach v 12 minimum value is slower than the time for v dd to reach 1.7 v, then pa0 could be asserted low externally (see figure 10 ). ? if v cap_1 and v cap_2 go below v 12 minimum value and v dd is higher than 1.7 v, then a reset must be asserted on pa0 pin. note: the minimum value of v 12 depends on the maximum frequency targeted in the application. dl9 %<3$66b5(* 9 &$3b 9 &$3b 3$ 9 9 '' 1567 9 '' $ssolfdwlrquhvhw vljqdorswlrqdo ([whuqdo9 &$3b srzhu vxsso\vxshuylvru ([wuhvhwfrqwuroohudfwlyh zkhq9 &$3b 0lq9 9
docid027589 rev 4 29/228 stm32f756xx functional overview 45 figure 9. startup in regulator off: slow v dd slope - power-down reset risen after v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). figure 10. startup in regulator off mode: fast v dd slope - power-down reset risen before v cap_1 /v cap_2 stabilization 1. this figure is valid whatever the internal reset mode (on or off). dli 9 '' wlph 0lq9 3'5 9ru9 9 &$3b 9 &$3b 9 1567 wlph 9 '' wlph 0lq9 9 &$3b 9 &$3b 9 3$dvvhuwhgh[whuqdoo\ 1567 wlph dlh 3'5 9ru9
functional overview stm32f756xx 30/228 docid027589 rev 4 2.18.3 regulator on/off and inte rnal reset on/off availability 2.19 real-time clock (rtc), back up sram and backup registers the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap ye ar), 30, and 31 days of the month. ? two programmable alarms. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to v bat mode. ? 17-bit auto-reload wakeup timer (wut) for periodic events with programmable resolution and period. the rtc and the 32 backup registers are supplied through a switch that takes power either from the v dd supply when present or from the v bat pin. the backup registers are 32-bit registers used to store 128 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. the rtc clock sources can be: ? a 32.768 khz external crystal (lse) ? an external resonator or oscillator(lse) ? the internal low-power rc oscillator (lsi, with typical frequency of 32 khz) ? the high-speed external clock (hse) divided by 32. table 4. regulator on/off and in ternal reset on/off availability package regulator on regulator off internal reset on internal reset off lqfp100 yes no yes no lqfp144, lqfp208 yes pdr_on set to v dd yes pdr_on set to vss tfbga100, lqfp176, wlcsp143, ufbga176, tfbga216 yes bypass_reg set to v ss yes bypass_reg set to v dd
docid027589 rev 4 31/228 stm32f756xx functional overview 45 the rtc is functional in v bat mode and in all lo w-power modes when it is clocked by the lse. when clocked by the lsi, the rtc is not functional in v bat mode, but is functional in all low-power modes. all rtc events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and wakeup the device from the low-power modes. 2.20 low-power modes the devices support three low-power modes to achieve the best compromise between low- power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode the stop mode achieves the lowest power consumption while retaining the contents of sram and registers. all clocks in the 1.2 v domain are stopped, the pll, the hsi rc and the hse crystal osc illators are disabled. the voltage regulator can be put either in main regulator mode (mr) or in low-power mode (lpr). both modes can be configured as follows (see table 5: voltage regulator modes in stop mode ): ? normal mode (default mode when mr or lpr is enabled) ? under-drive mode. the device can be woken up from the stop mo de by any of the exti line (the exti line source can be one of the 16 external lines , the pvd output, the rtc alarm / wakeup / tamper / time stamp events, the usb otg fs/hs wakeup or the ethernet wakeup and lptim1 asynchronous interrupt). ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.2 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, the sram and register conten ts are lost except for registers in the backup domain and the backup sram when selected. the device exits the standby mode when an external reset (nrst pin), an iwdg reset, a rising or falling edge on one of the 6 wkup pins (pa0, pa2, pc1, pc13, pi8, pi11), or an rtc alarm / wakeup / tamper /time stamp event occurs. the standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 v domain is controlled by an external power. table 5. voltage regulator modes in stop mode voltage regulator configuration main regulator (mr) low-power regulator (lpr) normal mode mr on lpr on under-drive mode mr in under-dri ve mode lpr in under-drive mode
functional overview stm32f756xx 32/228 docid027589 rev 4 2.21 v bat operation the v bat pin allows to power the device v bat domain from an external battery, an external supercapacitor, or from v dd when no external battery and an external supercapacitor are present. v bat operation is activated when v dd is not present. the v bat pin supplies the rtc, the backup registers and the backup sram. note: when the microcontroller is supplied from v bat , external interrupts and rtc alarm/events do not exit it from v bat operation. when pdr_on pin is connected to v ss (internal reset off), the v bat functionality is no more available and v bat pin should be connected to v dd . 2.22 timers and watchdogs the devices include two advanced-control time rs, eight general-purpose timers, two basic timers and two watchdog timers. all timer counters can be frozen in debug mode. table 6 compares the features of the advanced-c ontrol, general-purpose and basic timers.
docid027589 rev 4 33/228 stm32f756xx functional overview 45 table 6. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complem entary output max interfac e clock (mhz) max timer clock (mhz) (1) advance d-control tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes 108 216 general purpose tim2, tim5 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no 54 108/216 tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no 54 108/216 tim9 16-bit up any integer between 1 and 65536 no 2 no 108 216 tim10, tim11 16-bit up any integer between 1 and 65536 no 1 no 108 216 tim12 16-bit up any integer between 1 and 65536 no 2 no 54 108/216 tim13, tim14 16-bit up any integer between 1 and 65536 no 1 no 54 108/216 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 54 108/216 1. the maximum timer clock is either 108 or 216 mhz depending on timpre bit configuration in the rcc_dckcfgr register.
functional overview stm32f756xx 34/228 docid027589 rev 4 2.22.1 advanced-control timers (tim1, tim8) the advanced-control timers (tim1, tim8) can be seen as three-phase pwm generators multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead times. they can also be considered as complete general-purpose timers. their 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge- or center-aligned modes) ? one-pulse mode output if configured as standard 16-bit timers, they ha ve the same features as the general-purpose timx timers. if configured as 16-bit pwm generators, they have full modulation capability (0- 100%). the advanced-control timer can work togethe r with the timx timers via the timer link feature for synchronizat ion or event chaining. tim1 and tim8 support indepe ndent dma request generation. 2.22.2 general-purpose timers (timx) there are ten synchronizable general-purpose timers embedded in the stm32f756xx devices (see table 6 for differences). ? tim2, tim3, tim4, tim5 the stm32f756xx include 4 full-featured g eneral-purpose timers: tim2, tim5, tim3, and tim4.the tim2 and tim5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. the tim3 and tim4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. they all feature 4 independent channels for input capture/ou tput compare, pwm or one-pul se mode output. this gives up to 16 input capture/output comp are/pwms on the largest packages. the tim2, tim3, tim4, tim5 general-purpose timers can work together, or with the other general-purpose timers and the advanc ed-control timers tim1 and tim8 via the timer link feature for synchronization or event chaining. any of these general-purpose timers can be used to generate pwm outputs. tim2, tim3, tim4, tim5 all have indepen dent dma request generation. they are capable of handling quadrature (incremental ) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. ? tim9, tim10, tim11, ti m12, tim13, and tim14 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim10, tim11, tim13, and tim14 feature one independent channel, whereas tim9 and tim12 have two independent channels fo r input capture/output compare, pwm or one-pulse mode output. they can be synchronized with the tim2, tim3, tim4, tim5 full-featured general-purpose timers. they can also be used as simple time bases.
docid027589 rev 4 35/228 stm32f756xx functional overview 45 2.22.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger and waveform generation. they can also be used as a generic 16-bit time base. tim6 and tim7 support indepe ndent dma request generation. 2.22.4 low-power timer (lptim1) the low-power timer has an independent clock and is running also in stop mode if it is clocked by lse, lsi or an external clock. it is able to wakeup the devices from stop mode. this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous / one-shot mode ? selectable software / hardware input trigger ? selectable clock source: ? internal clock source: l se, lsi, hsi or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by the pulse counter application) ? programmable digital glitch filter ? encoder mode 2.22.5 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. it is hardware- or software-configurable through the option bytes. 2.22.6 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free-running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 2.22.7 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. it features: ? a 24-bit downcounter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source.
functional overview stm32f756xx 36/228 docid027589 rev 4 2.23 inter-integrated circuit interface (i 2 c) the device embeds 4 i2c. refer to table 7: i2c implementation for the features implementation. the i 2 c bus interface handles communication be tween the microcontroller and the serial i 2 c bus. it co ntrols all i 2 c bus-specific sequencing, protocol, arbitration and timing. the i2c peripheral supports: ? i 2 c-bus specification and user manual re v. 5 compatibility: ? slave and master modes , multimaster capability ? standard-mode (sm), with a bitrate up to 100 kbit/s ? fast-mode (fm), with a bitrate up to 400 kbit/s ? 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses ? programmable setup and hold times ? optional clock stretching ? system management bus (smbus) spec ification rev 2.0 compatibility: ? hardware pec (packet error checking) generation and verification with ack control ? address resolution protocol (arp) support ? smbus alert ? power system management protocol (pmbus tm ) specification rev 1.1 compatibility ? independent clock: a choice of independent clock sources allowing the i2c communication speed to be independent from the pclk reprogramming. ? programmable analog and digital noise filters ? 1-byte buffer with dma capability table 7. i2c implementation i2c features (1) 1. x: supported i2c1 i2c2 i2c3 i2c4 standard-mode (up to 100 kbit/s) x x x x fast-mode (up to 400 kbit/s) x x x x programmable analog and digital noise filters x x x x smbus/pmbus hardware support x x x x independent clock x x x x
docid027589 rev 4 37/228 stm32f756xx functional overview 45 2.24 universal synchronous/asynch ronous receiver transmitters (usart) the device embeds usart. refer to ta bl e 8: usart implementation for the features implementation. the universal synchronous asynchronous receiver transmitter (usart) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard nrz asynchronous serial data format. the usart peripheral supports: ? full-duplex asynchronous communications ? configurable oversamp ling method by 16 or 8 to gi ve flexibility be tween speed and clock tolerance ? dual clock domain allowing convenient baud rate programming independent from the pclk reprogramming ? a common programmable transmit and receive baud rate of up to 27 mbit/s when usart clock source is system clock frequenc y (max is 216 mhz) and oversampling by 8 is used. ? auto baud rate detection ? programmable data word length (7 or 8 or 9 bits) word length ? programmable data order with msb-first or lsb-first shifting ? programmable parity (odd, even, no parity) ? configurable stop bits (1 or 1.5 or 2 stop bits) ? synchronous mode and clock output for synchronous communications ? single-wire half-duplex communications ? separate signal polarity control for transmission and reception ? swappable tx/rx pin configuration ? hardware flow control for mo dem and rs-485 transceiver ? multiprocessor communications ? lin master synchronous break send capability and lin slav e break detection capability ? irda sir encoder decoder supporting 3/16 bit duration for normal mode ? smartcard mode ( t=0 and t=1 asynchronous protocols for smartcards as defined in the iso/iec 7816-3 standard ) ? support for modbus communication the table below summarizes the implementation of all u(s)arts instances table 8. usart implementation features (1) usart1/2/3/6 uart4/5/7/8 data length 7, 8 and 9 bits hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x -
functional overview stm32f756xx 38/228 docid027589 rev 4 2.25 serial peripheral interface (spi)/inter- integrated sound interfaces (i2s) the devices feature up to six spis in slave and master modes in full-duplex and simplex communication modes. spi1, spi4, spi5, and spi6 can communicate at up to 50 mbits/s, spi2 and spi3 can communicate at up to 25 mbit/s. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. the spi interfaces support nss pulse mode, ti mode and hardware crc calculation. all spis can be served by the dma controller. three standard i 2 s interfaces (multiplexed with spi1, spi2 and spi3) are available. they can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit reso lution as an input or output channel. audio sampling frequencies from 8 khz up to 192 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mo de, the master clock can be output to the external dac/codec at 256 ti mes the sampling frequency. all i2sx can be served by the dma controller. 2.26 serial audio interface (sai) the devices embed two serial audio interfaces. the serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their fifo. many audio protocols are supported by each block: i2s standards, lsb or msb-justifie d, pcm/dsp, tdm, ac?97 and spdif output, supporting audio sampling freq uencies from 8 khz up to 19 2 khz. both subblocks can be configured in master or in slave mode. in master mode, the master clock can be output to the external dac/codec at 256 times of the sampling frequency. the two sub-blocks can be configured in synchronous mode when full-duplex mode is required. smartcard mode x - single-wire half-duplex communication x x irda sir endec block x x lin mode x x dual clock domain x x receiver timeout interrupt x x modbus communication x x auto baud rate detection x x driver enable x x 1. x: supported. table 8. usart implementation (continued) features (1) usart1/2/3/6 uart4/5/7/8
docid027589 rev 4 39/228 stm32f756xx functional overview 45 sai1 and sai2 can be served by the dma controller 2.27 spdifrx receiver interface (spdifrx) the spdifrx peripheral, is designed to receiv e an s/pdif flow compliant with iec-60958 and iec-61937. these standards support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as those defined by dolby or dts (up to 5.1). the main features of the spdifrx are the following: ? up to 4 inputs available ? automatic symbol rate detection ? maximum symbol rate: 12.288 mhz ? stereo stream from 32 to 192 khz supported ? supports audio iec-60958 and iec-61937, consumer applications ? parity bit management ? communication using dma for audio samples ? communication using dma for contro l and user channel information ? interrupt capabilities the spdifrx receiver provides all the necessa ry features to detect the symbol rate, and decode the incoming data stream. the user can select the wanted spdif input, and when a valid signal will be available, the spdifrx will re-sample the incoming signal, decode the manchester stream, recognize frames, sub-fram es and blocks elements. it delivers to the cpu decoded data, and associated status flags. the spdifrx also offers a signal named spdif_ frame_sync, which toggles at the s/pdif sub-frame rate that will be used to compute the exact sample ra te for clock drift algorithms. 2.28 audio pll (plli2s) the devices feature an additional dedicated pll for audio i 2 s and sai applications. it allows to achieve error-free i 2 s sampling clock accuracy witho ut compromising on the cpu performance, while using usb peripherals. the plli2s configuration can be modified to manage an i 2 s/sai sample rate change without disabling the main pll (pll) used for cpu, usb and ethernet interfaces. the audio pll can be programmed with very low error to obtain sampling rates ranging from 8 khz to 192 khz. in addition to the audio pll, a master clock input pin can be used to synchronize the i 2 s/sai flow with an external pll (or codec output).
functional overview stm32f756xx 40/228 docid027589 rev 4 2.29 audio and lcd pll(pllsai) an additional pll dedicated to audio and lc d-tft is used for sai1 peripheral in case the plli2s is programmed to achieve another audio sampling frequency (49.152 mhz or 11.2896 mhz) and the audio application requires both sampling frequencies simultaneously. the pllsai is also used to generate the lcd-tft clock. 2.30 sd/sdio/mmc card ho st interface (sdmmc) an sdmmc host interface is available, that su pports multimediacard system specification version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. the interface allows data transfer at up to 50 mhz, and is compliant with the sd memory card specification version 2.0. the sdmmc card specification version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. the current version supports only one sd/s dmmc/mmc4.2 card at any one time and a stack of mmc4.1 or previous. the sdmmc can be served by the dma controller 2.31 ethernet mac interface with dedicated dma and ieee 1588 support the devices provide an ieee- 802.3-2002-compliant media access controller (mac) for ethernet lan communications through an industry-standard medium-independent interface (mii) or a reduced medium-independent interfac e (rmii). the microcontroller requires an external physical interface device (phy) to co nnect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connec ted to the device mii port using 17 signals for mii or 9 signals for rmii, and can be clocked using the 25 mhz (mii) from the microcontroller. the devices include the following features: ? support of 10 and 100 mbit/s rates ? dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors ? tagged mac frame support (vlan support) ? half-duplex (csma/cd) and full-duplex operation ? mac control sublayer (control frames) support ? 32-bit crc generation and removal ? several address filtering modes for physic al and multicast address (multicast and group addresses) ? 32-bit status code for each transmitted or received frame ? internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes. ? supports hardware ptp (precision time protocol) in accordance with ieee 1588 2008 (ptp v2) with the time stamp compar ator connected to the tim2 input ? triggers interrupt when system time becomes greater than target time
docid027589 rev 4 41/228 stm32f756xx functional overview 45 2.32 controller area network (bxcan) the two cans are compliant with the 2.0a and b (a ctive) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit id entifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). 256 bytes of sram are allocated for each can. 2.33 universal serial bus on -the-go full-speed (otg_fs) the device embeds an usb otg full-speed de vice/host/otg peripher al with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg controller requires a dedicat ed 48 mhz clock that is generated by a p ll connected to the hse oscillator. the major features are: ? combined rx and tx fifo size of 1.28 kbytes with dynamic fifo sizing ? support of the session request protocol (s rp) and host negotiat ion protocol (hnp) ? 1 bidirectional control endpoint + 5 in endpoints + 5 out endpoints ? 12 host channels with periodic out support ? software configurable to otg1.3 and otg2.0 modes of operation ? usb 2.0 lpm (link power management) support ? internal fs otg phy support ? hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.34 universal serial bus on -the-go high-speed (otg_hs) the device embeds a usb otg high-speed (up to 480 mb/s) device/host/otg peripheral. the usb otg hs supports both full-speed and high-speed operations. it integrates the transceivers for full-speed operation (12 mb/s) and features a utmi low-pin interface (ulpi) for high-speed operation (480 mb/s). when using the usb otg hs in hs mode, an external phy device connecte d to the ulpi is required. the usb otg hs peripheral is compliant wit h the usb 2.0 specification and with the otg 2.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg controller requires a dedicated 48 mhz clock that is generated by a p ll connected to the hse oscillator.
functional overview stm32f756xx 42/228 docid027589 rev 4 the major features are: ? combined rx and tx fifo size of 4 kbytes with dynamic fifo sizing ? support of the session request protocol (s rp) and host negotiat ion protocol (hnp) ? 8 bidirectional endpoints ? 16 host channels with periodic out support ? software configurable to otg1.3 and otg2.0 modes of operation ? usb 2.0 lpm (link power management) support ? internal fs otg phy support ? external hs or hs otg operation suppor ting ulpi in sdr mode. the otg phy is connected to the microcontroller ulpi port through 12 signals. it can be clocked using the 60 mhz output. ? internal usb dma ? hnp/snp/ip inside (no need for any external resistor) ? for otg/host modes, a power switch is needed in case bus-powered devices are connected 2.35 high-definition multimedia interface (hdmi) - consumer electronics control (cec) the device embeds a hdmi-cec controller that provides hardware support for the consumer electronics control (cec) protoc ol (supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. it has a clock domain independent from the cpu clock, allowing the hdmi-cec controller to wakeup the mcu from stop mode on data reception. 2.36 digital camera interface (dcmi) the devices embed a camera interface that can connect with camera modules and cmos sensors through an 8-bit to 14-bit parallel interface, to receive video data. the camera interface can sustain a data transfer rate up to 54 mbyte/s at 54 mhz. it features: ? programmable polarity for the input pixel clock and synchronization signals ? parallel data communication can be 8-, 10-, 12- or 14-bit ? supports 8-bit progressive video monochrome or raw bayer format, ycbcr 4:2:2 progressive video, rgb 565 progressive video or compressed data (like jpeg) ? supports continuous mode or snapshot (a single frame) mode ? capability to automatically crop the image 2.37 cryptograp hic acceleration the devices embed a cryptographic accelerator. this cryptographic accelerator provides a set of hardware acceleration for the advanced cryptographic algorithms usually needed to
docid027589 rev 4 43/228 stm32f756xx functional overview 45 provide confidentiality, authentication, data in tegrity and non repudiation when exchanging messages with a peer. ? these algorithms consists of: encryption/decryption ? des/tdes (data encryption standard/triple data encryption standard): ecb (electronic codebook) and cbc (cipher block chaining) chaining algorithms, 64-, 128- or 192-bit key ? aes (advanced encryption standard): ecb, cbc, gcm, ccm, and ctr (counter mode) chaining algorithms, 128, 192 or 256-bit key universal hash ? sha-1 and sha-2 (secure hash algorithms) ?md5 ?hmac the cryptographic accelerator supports dma request generation. 2.38 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. 2.39 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain, with or without pull-up or pull-down), as input (f loating, with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high-current -capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. the i/o configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling a llowing maximum i/o toggling up to 108 mhz. 2.40 analog-to-digital converters (adcs) three 12-bit analog-to-digital converters are embedded and each adc shares up to 16 external channels, performing conversions in the single-shot or scan mode. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted vo ltage is outside the programmed thresholds. to synchronize a/d conversion and timers, t he adcs could be triggered by any of tim1, tim2, tim3, tim4, tim5, or tim8 timer.
functional overview stm32f756xx 44/228 docid027589 rev 4 2.41 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 1.7 v and 3.6 v. the temperature sensor is internally connected to the same input channel as v bat , adc1_in18, which is used to convert the sensor output voltage into a digital value. when the temperature sensor and v bat conversion are enabled at the same time, only v bat conversion is performed. as the offset of the temperature sensor varies fr om chip to chip due to process variation, the internal temperature sensor is mainly suitab le for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.42 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. this dual digital interface supports the following features: ? two dac converters: one for each output channel ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? input voltage reference v ref+ eight dac trigger inputs are used in the device. the dac channels are triggered through the timer update outputs that are also connected to different dma streams. 2.43 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp.
docid027589 rev 4 45/228 stm32f756xx functional overview 45 2.44 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f756xx through a small number of etm pi ns to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host co mputer using usb, ethernet, or any other high-speed channel. real-time instru ction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools.
pinouts and pin description stm32f756xx 46/228 docid027589 rev 4 3 pinouts and pin description figure 11. stm32f756vx lqfp100 pinout 2. the above figure shows the package top view. ?? ?? ? ? ?? ?e ?? ?? ? ? ?? ?? ? ? ?? ?e ?? ?? ? ? ? ? ? ? e ? ? ? ? ? e ? ? ? ? ? ?? ?? ?e ?? ? e ? ? ? ? ? e ? ? ?? ?? ? ? ?? ?e ?? ?? ? w? w? we w? w werk^??z/e w?rk^??zkhd s^^ s w,rk^z/e w w w? w? s^^ sz&= s s s^^ sw? w? w? w w s^^ s we w w? w w? w? sw s s s^^ w w w? we w? w? w w w? w w ? ? ?? ?? ? ? ?? ?? ?e ?? ? ? ?? ?? e e e? e? ee e? e e e? e? ? 06y9 /4)3 w?red/zddw w,rk^zkhd wrt<hw w w? w? w? w w we w w? w? we w? w w w w? w s^^ w? w w? w? we w? w? w? w w? we w? w? w? w w w? w? w? we w w w? w? kkd w w w? we w? sd ez^d
docid027589 rev 4 47/228 stm32f756xx pinouts and pin description 89 figure 12. stm32f756vx tfbga100 ballout 1. the above figure shows the package top view. 06y9 $ % ( ' & ) * + - . 3& 1567 3+ 3+ 3& 9''$ 966 9'' 3& 966 9%$7 9'' 3& 3$ 3$ 3$ 3( 3( 3( 3( 3( 3$ 3$ 3$ 3% 3% 3% 3% 3% 3( 3% 3' 3% 3' 3% 3$ 3& 3& 3' 3' 3' 3% 3% 3$ 3& 3$ 3$ 3& 3' 3' 3' 3$ 3$ 3$ 3$ 3& 3% 3' 3' 3& 966$ 3& 3$ 3& 3$ 9'' 3& 9'' 3% 9''86% 3( 3'5b21 3( 9&$3b 3' 3& 3' 3& 3% 3& 3( 3( 3( 3( 3( 3% %227 3' 3' 3' 3' 966 966 %<3$66 5(* 9&$3b 3% 3( 3( 3% 3(
pinouts and pin description stm32f756xx 48/228 docid027589 rev 4 figure 13. stm32f756zx wlcsp143 ballout 1. the above figure shows the package top view. 06y9 $ % & ' ( ) * + - . / 0 1 9%$7 3'5b 21 3( 3& 3& 3) 3) 3) 3+ 3& 95() 3$ %<3$66 b5(* 3( 3( 3( 3& 9'' 3) 3) 3+ 3& 966$ 9''$ 3$ 3$ 3% 3% 3* 3* 3' 3' 3' 3& 9'' 3% 3% 3% 3* 3' 3' 3' 3& 3$ %227 3% 3% 3* 9'' 3' 3& 3$ 9'' 3( 3( 9'' 3$ 3$ 3$ 966 9&$3b 3) 3( 966 9'' 3* 3& 3& 3$ 3$ 3) 3) 3) 3* 966 3' 3& 3& 3$ 3) 3) 9'' 3* 3* 3* 3* 3* 9''86% 1567 3& 966 3' 3' 3' 966 966 3* 3& 3) 3) 3* 3( 3% 3' 3' 3$ 3$ 3% 9'' 9'' 9'' 9'' 3( 3% 3' 3* 3$ 3$ 3% 3( 3( 3( 3' 9'' 3$ 3& 3) 3) 3( 3( 3% 3% 3' 3& 3% 3) 3* 3( 3( 3% 9&$3b 3% 3*
docid027589 rev 4 49/228 stm32f756xx pinouts and pin description 89 figure 14. stm32f756zx lqfp144 pinout 1. the above figure shows the package top view. 9 '' 3'5b21 3( 3( 3% 3% %22 7 3% 3% 3% 3% 3% 3* 9 '' 9 66 3* 3* 3* 3* 3* 3* 3' 3' 9 '' 9 66 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 3( 9 '' 3( 9 66 3( 3( 3$ 3( 3$ 9%$7 3$ 3& 3$ 3& 3$ 3& 3$ 3) 3& 3) 3& 3) 3& 3) 3& 3) 9 ''86% 3) 9 66 9 66 3* 9 '' 3* 3) 3* 3) 3* 3) 3* 3) 3* 3) 3* 3+ 3' 3+ 3' 15 67 9 '' 3& 9 66 3& 3' 3& 3' 3& 3' 9 66$ 3' 9 '' 3' 9 5() 3' 9 ''$ 3% 3$ 3% 3$ 3% 3$ 3% 3$ 9 66 9 '' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 9 '' 3) 3) 3) 3* 3* 3( 3( 3( 9 66 9 '' 3( 3( 3( 3( 3( 3( 3% 3% 9 '' /4)3 9 &$3b 9 66 dlf 9 &$3b
pinouts and pin description stm32f756xx 50/228 docid027589 rev 4 figure 15. stm32f756ix lqfp176 pinout 1. the above figure shows the package top view. -36 0$2?/. 6 $$ 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6 $$ 6 33 0' 0' 0' 0' 0' 0' 0$ 0$ 6 $$ 6 33 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0) 0) 0% 6 $$ 0% 6 33 0% 0% 0! 0% 0! 6"!4 0! 0) 0! 0# 0! 0# 0! 0& 0# 0& 0# 0& 0# 0& 0# 0& 6 $$53" 0& 6 33 0' 0' 0& 0' 0& 0' 0& 0' 0& 0' 0& 0' 0( 0$ 0( 0$ .234 6 $$ 0# 6 33 0# 0$ 0# 0$ 0# 0$ 0$ 0$ 62%& 0$ 0" 0! 0" 0! 0" 0! 0" 0! "90!33?2%' 6 $$ 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 633 6 $$ 0& 0& 0& 0' 0' 0% 0% 0% 6 33 6 $$ 0% 0% 0% 0% 0% 0% 0" 0" 6 #!0? 6 $$ ,1&0 6 #!0? 0) 0! 0! 6 $$ 6 33 0) 0) 0) 0( 0( 0( 0( 0( 0( 0( 0( 0) 0) 0( 0( 0( 6 $$ 6 33 0( 0# 0) 0) 0) 633 0( 0( 6$$ 633 6$$ 6$$ 633! 6$$!
docid027589 rev 4 51/228 stm32f756xx pinouts and pin description 89 figure 16. stm32f756bx lqfp208 pinout 1. the above figure shows the package top view. 069 w/ w/ w/? w/e s s^^ w w w? w? w w w? we w? w'? w< w< wy&w?? ? ? ?? ?? ? ? ?? ?? ?e ?? ? ? ?? ?? e e e? e? ee e? e e e? e? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? e ? ? ? ? ? e ? ? ? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? ?? ?? ?e ?? ? ? ?? ?? ? ? e w? w? we w? w sd w/? w? we w? w/? w/ w/ s^^ s w& w& w&? w/? w/? w/e w&? w&e w&? s^^ s w& w& w&? w&? w& w, w, ez^d w w w? w? s s^^ sz&= s w w w? w,? w,? w,e w,? w? s^^ s w/? w/ w/ w,? w,e w,? s s^^ swz? w? w? w w w? w? w? w? w w sh^ s^^ w'? w' w' w'? w'e w'? w'? w pinouts and pin description stm32f756xx 52/228 docid027589 rev 4 figure 17. stm32f756ix ufbga176 ballout 1. the above figure shows the package top view. aid !0%0% 0% 0% 0" 0" 0' 0' 0" 0" 0$ 0# 0! 0! 0! "0%0% 0% 0" 0" 0" 0' 0' 0' 0' 0$ 0$ 0# 0# 0! # 6"!4 0) 0) 0) 0$2?/. 6$$ 6$$ 6$$ 6$$ 0' 0$ 0$ 0) 0) 0! $ 0# 0) 0) 0) "//4 633 633 633 0$ 0$ 0$ 0( 0) 0! % 0# 0& 0) 0) 0( 0( 0) 0! &0# 633 6$$ 0( 633 633 633 633 633 633 6#!0 0# 0! ' 0( 633 6$$ 0( 633 633 633 633 633 633 6$$ 0# 0# ( 0( 0& 0& 0( 633 633 633 633 633 633 6$$53" 0' 0# * .234 0& 0( 633 633 633 633 633 6$$ 6$$ 0' 0' + 0& 0& 0& 6$$ 633 633 633 633 633 0( 0' 0' 0' , 0& 0& 0& "90!33? 2%' 0( 0( 0$ 0' -633!0# 0& 0# 0# 0# 0" 0' 633 633 6#!0? 0( 0( 0( 0$ 0$ .62%& 0! 0! 0# 0& 0' 6$$ 6$$ 6$$ 0% 0( 0$ 0$ 0$ 062%& 0! 0! 0! 0# 0& 0& 0% 0% 0% 0% 0" 0" 0$ 0$ 2 6$$! 0! 0! 0" 0" 0& 0& 0% 0% 0% 0% 0" 0" 0" 0" 633 0!
docid027589 rev 4 53/228 stm32f756xx pinouts and pin description 89 figure 18. stm32f756nx tfbga216 ballout 1. the above figure shows the package top view. 06y9 $ 3( 3( 3( 3* 3( 3( 3% 3% 3% 3% 3' 3& 3$ 3$ 3$ % 3( 3( 3* 3% 3% 3% 3* 3* 3- 3- 3' 3' 3& 3& 3$ & 9%$7 3, 3, 3. 3. 3. 3* 3* 3- 3' 3' 3' 3, 3, 3$ ' 3& 3) 3, 3, 3, 3, 3. 3. 3* 3- 3' 3' 3+ 3, 3$ ( 3& 3) 3, 3, 3'5 b21 %227 9'' 9'' 9'' 9'' 9&$3b 3+ 3+ 3, 3$ ) 3& 966 3, 9'' 9'' 966 966 9'' 3. 3. 3& 3$ * 3+ 3) 3, 3, 9'' 966 9''86% 3- 3. 3& 3& + 3+ 3, 3+ 9'' 966 966 9'' 3- 3- 3* 3& - 1567 3) 3+ 3+ 9'' 966 966 9'' 3- 3- 3* 3* . 3) 3) 3) 3+ 9'' 966 966 966 966 966 9'' 3- 3' 3% 3' / 3) 3) 3) 3& %<3$66 5(* 966 9'' 9'' 9'' 9'' 9&$3b 3' 3% 3' 3' 0 966$ 3& 3& 3& 3% 3) 3* 3) 3- 3' 3' 3* 3* 3- 3+ 1 95() 3$ 3$ 3$ 3& 3) 3* 3- 3( 3' 3* 3* 3+ 3+ 3+ 95() 3$ 3$ 3$ 3& 3) 3- 3) 3( 3( 3( 3% 3+ 3+ 3+ 3$ 3$ 3% 3% 3- 3- 3( 3( 3( 3( 3( 3% 3% 3% 966 3) 3 5 9''$ 966 966 966
pinouts and pin description stm32f756xx 54/228 docid027589 rev 4 table 9. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tta 3.3 v tolerant i/o directly connected to adc b dedicated boot pin rst bidirectional reset pin with weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers table 10. stm32f756xx pin and ball definition pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216 1 a3 d8 1 a2 1 1 a3 pe2 i/o ft - traceclk, spi4_sck, sai1_mclk_a, quadspi_bk1_io2, eth_mii_txd3, fmc_a23, eventout - 2 b3 c10 2 a1 2 2 a2 pe3 i/o ft - traced0, sai1_sd_b, fmc_a19, eventout - 3 c3 b11 3 b1 3 3 a1 pe4 i/o ft - traced1, spi4_nss, sai1_fs_a, fmc_a20, dcmi_d4, lcd_b0, eventout -
docid027589 rev 4 55/228 stm32f756xx pinouts and pin description 89 4 d3 d9 4 b2 4 4 b1 pe5 i/o ft - traced2, tim9_ch1, spi4_miso, sai1_sck_a, fmc_a21, dcmi_d6, lcd_g0, eventout - 5 e3 e8 5 b3 5 5 b2 pe6 i/o ft - traced3, tim1_bkin2, tim9_ch2, spi4_mosi, sai1_sd_a, sai2_mck_b, fmc_a22, dcmi_d7, lcd_g1, eventout - - - - - - - - g6 vss s - - - - -- -----f5vdds-- - - 6b2c116c16 6c1 vbat s-- - - - - - - d2 7 7 c2 pi8 i/o ft (2) (3) eventout rtc_tamp2/ rtc_ts,wk up5 7a2d107d18 8d1 pc13i/oft (2) (3) eventout rtc_tamp1/ rtc_ts/rtc _out,wkup 4 8a1d118e19 9e1 pc14- osc32_i n(pc14) i/o ft (2) (3) eventout osc32_in 9b1e119f11010f1 pc15- osc32_ out(pc 15) i/o ft (2) (3) eventout osc32_out -- -----g5vdds-- - - - - - - d3 11 11 e4 pi9 i/o ft - can1_rx, fmc_d30, lcd_vsync, eventout - - - - - e3 12 12 d5 pi10 i/o ft - eth_mii_rx_er, fmc_d31, lcd_hsync, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 56/228 docid027589 rev 4 - - - - e4 13 13 f3 pi11 i/o ft - otg_hs_ulpi_dir, eventout wkup6 - - e7 - f2 14 14 f2 vss s - - - - - - e10 - f3 15 15 f4 vdd s - - - - - - f1110e21616d2 pf0 i/oft- i2c2_sda, fmc_a0, eventout - - - e9 11 h3 17 17 e2 pf1 i/o ft - i2c2_scl, fmc_a1, eventout - - - f1012h21818g2 pf2 i/oft- i2c2_smba, fmc_a2, eventout - - - - - - - 19 e3 pi12 i/o ft - lcd_hsync, eventout - - - - - - - 20 g3 pi13 i/o ft - lcd_vsync, eventout - - - - - - - 21 h3 pi14 i/o ft - lcd_clk, eventout - - - g11 13 j2 19 22 h2 pf3 i/o ft - fmc_a3, eventout adc3_in9 - - f9 14 j3 20 23 j2 pf4 i/o ft - fmc_a4, eventout adc3_in14 - - f8 15 k3 21 24 k3 pf5 i/o ft - fmc_a5, eventout adc3_in15 10 c2 h7 16 g2 22 25 h6 vss s - - - - 11d2 - 17g323 26h5 vdd s - - - - --g1018k22427k2pf6i/oft- tim10_ch1, spi5_nss, sai1_sd_b, uart7_rx, quadspi_bk1_io3, eventout adc3_in4 - - f7 19 k1 25 28 k1 pf7 i/o ft - tim11_ch1, spi5_sck, sai1_mclk_b, uart7_tx, quadspi_bk1_io2, eventout adc3_in5 table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 57/228 stm32f756xx pinouts and pin description 89 - - h1120l32629l3 pf8 i/oft- spi5_miso, sai1_sck_b, uart7_rts, tim13_ch1, quadspi_bk1_io0, eventout adc3_in6 - - g8 21 l2 27 30 l2 pf9 i/o ft - spi5_mosi, sai1_fs_b, uart7_cts, tim14_ch1, quadspi_bk1_io1, eventout adc3_in7 - - g9 22 l1 28 31 l1 pf10 i/o ft - dcmi_d11, lcd_de, eventout adc3_in8 12c1j1123g129 32g1 ph0- osc_in( ph0) i/o ft - eventout osc_in (4) 13 d1 h10 24 h1 30 33 h1 ph1- osc_ou t(ph1) i/o ft - eventout osc_out (4) 14 e1 h9 25 j1 31 34 j1 nrst i/o rs t -- - 15 f1 h8 26 m2 32 35 m2 pc0 i/o ft (4) sai2_fs_b, otg_hs_ulpi_stp, fmc_sdnwe, lcd_r5, eventout adc123_in1 0 16 f2k1127m333 36m3 pc1 i/oft (4) traced0, spi2_mosi/i2s2_sd, sai1_sd_a, eth_mdc, eventout adc123_in1 1, rtc_tamp3, wkup3 17e2j1028m434 37m4 pc2 i/oft (4) spi2_miso, otg_hs_ulpi_dir, eth_mii_txd2, fmc_sdne0, eventout adc123_in1 2 table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 58/228 docid027589 rev 4 18 f3 j9 29 m5 35 38 l4 pc3 i/o ft (4) spi2_mosi/i2s2_sd, otg_hs_ulpi_nxt, eth_mii_tx_clk, fmc_sdcke0, eventout adc123_in1 3 - - g7 30 g3 36 39 j5 vdd s - - - - - - - - - - - j6 vss s - - - - 19 g1 k10 31 m1 37 40 m1 vssa s - - - - - - - - n1 - - n1 vref- s - - - - 20 - l11 32 p1 38 41 p1 vref+ s - - - - 21 h1 l10 33 r1 39 42 r1 vdda s - - - - 22 g2 k9 34 n3 40 43 n3 pa0- wkup(p a0) i/o ft (5) tim2_ch1/tim2_etr, tim5_ch1, tim8_etr, usart2_cts, uart4_tx, sai2_sd_b, eth_mii_crs, eventout adc123_in0, wkup1 (4) 23 h2 k8 35 n2 41 44 n2 pa1 i/o ft (4) tim2_ch2, tim5_ch2, usart2_rts, uart4_rx, quadspi_bk1_io3, sai2_mck_b, eth_mii_rx_clk/eth_ rmii_ref_clk, lcd_r2, eventout adc123_in1 24 j2 l9 36 p2 42 45 p2 pa2 i/o ft (4) tim2_ch3, tim5_ch3, tim9_ch1, usart2_tx, sai2_sck_b, eth_mdio, lcd_r1, eventout adc123_in2, wkup2 - - - - f4 43 46 k4 ph2 i/o ft lptim1_in2, quadspi_bk2_io0, sai2_sck_b, eth_mii_crs, fmc_sdcke0, lcd_r0, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 59/228 stm32f756xx pinouts and pin description 89 - - - - g4 44 47 j4 ph3 i/o ft - quadspi_bk2_io1, sai2_mck_b, eth_mii_col, fmc_sdne0, lcd_r1, eventout - - - - - h4 45 48 h4 ph4 i/o ft - i2c2_scl, otg_hs_ulpi_nxt, eventout - - - - - j4 46 49 j3 ph5 i/o ft - i2c2_sda, spi5_nss, fmc_sdnwe, eventout - 25 k2 m11 37 r2 47 50 r2 pa3 i/o ft (4) tim2_ch4, tim5_ch4, tim9_ch2, usart2_rx, otg_hs_ulpi_d0, eth_mii_col, lcd_b5, eventout adc123_in3 26 j1 - 38 - - 51 k6 vss s - - - - -e6n11-l448-l5 bypass _reg ift- - - 27 k1 j8 39 k4 49 52 k5 vdd s - - - - 28 g3 m10 40 n4 50 53 n4 pa4 i/o tt a (4) spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, usart2_ck, otg_hs_sof, dcmi_hsync, lcd_vsync, eventout adc12_in4, dac_out1 29 h3 m9 41 p4 51 54 p4 pa5 i/o tt a (4) tim2_ch1/tim2_etr, tim8_ch1n, spi1_sck/i2s1_ck, otg_hs_ulpi_ck, lcd_r4, eventout adc12_in5, dac_out2 30 j3 n10 42 p3 52 55 p3 pa6 i/o ft (4) tim1_bkin, tim3_ch1, tim8_bkin, spi1_miso, tim13_ch1, dcmi_pixclk, lcd_g2, eventout adc12_in6 table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 60/228 docid027589 rev 4 31 k3 l8 43 r3 53 56 r3 pa7 i/o ft (4) tim1_ch1n, tim3_ch2, tim8_ch1n, spi1_mosi/i2s1_sd, tim14_ch1, eth_mii_rx_dv/eth_r mii_crs_dv, fmc_sdnwe, eventout adc12_in7 32 g4 m8 44 n5 54 57 n5 pc4 i/o ft (4) i2s1_mck, spdifrx_in2, eth_mii_rxd0/eth_rm ii_rxd0, fmc_sdne0, eventout adc12_in14 33 h4 n9 45 p5 55 58 p5 pc5 i/o ft (4) spdifrx_in3, eth_mii_rxd1/eth_rm ii_rxd1, fmc_sdcke0, eventout adc12_in15 - - j7 - - - 59 l7 vdd s - - - - - - - - - - 60 l6 vss s - - - - 34 j4 n8 46 r5 56 61 r5 pb0 i/o ft (4) tim1_ch2n, tim3_ch3, tim8_ch2n, uart4_cts, lcd_r3, otg_hs_ulpi_d1, eth_mii_rxd2, eventout adc12_in8 35 k4 k7 47 r4 57 62 r4 pb1 i/o ft (4) tim1_ch3n, tim3_ch4, tim8_ch3n, lcd_r6, otg_hs_ulpi_d2, eth_mii_rxd3, eventout adc12_in9 36 g5 l7 48 m6 58 63 m5 pb2 i/o ft - sai1_sd_a, spi3_mosi/i2s3_sd, quadspi_clk, eventout - - - - - - - 64 g4 pi15 i/o ft - lcd_r0, eventout - - - - - - - 65 r6 pj0 i/o ft - lcd_r1, eventout - - - - - - - 66 r7 pj1 i/o ft - lcd_r2, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 61/228 stm32f756xx pinouts and pin description 89 - - - - - - 67 p7 pj2 i/o ft - lcd_r3, eventout - - - - - - - 68 n8 pj3 i/o ft - lcd_r4, eventout - - - - - - - 69 m9 pj4 i/o ft - lcd_r5, eventout - - - m7 49 r6 59 70 p8 pf11 i/o ft - spi5_mosi, sai2_sd_b, fmc_sdnras, dcmi_d12, eventout - - - n7 50 p6 60 71 m6 pf12 i/o ft - fmc_a6, eventout - - - - 51m861 72 k7 vss s - - - - -- -52n86273l8vdds-- - - - - k6 53 n6 63 74 n6 pf13 i/o ft - i2c4_smba, fmc_a7, eventout - - - l6 54 r7 64 75 p6 pf14 i/o ft - i2c4_scl, fmc_a8, eventout - - - m6 55 p7 65 76 m8 pf15 i/o ft - i2c4_sda, fmc_a9, eventout - - - n6 56 n7 66 77 n7 pg0 i/o ft - fmc_a10, eventout - - - k5 57 m7 67 78 m7 pg1 i/o ft - fmc_a11, eventout - 37 h5 l5 58 r8 68 79 r8 pe7 i/o ft - tim1_etr, uart7_rx, quadspi_bk2_io0, fmc_d4, eventout - 38 j5 m5 59 p8 69 80 n9 pe8 i/o ft - tim1_ch1n, uart7_tx, quadspi_bk2_io1, fmc_d5, eventout - 39 k5 n5 60 p9 70 81 p9 pe9 i/o ft - tim1_ch1, uart7_rts, quadspi_bk2_io2, fmc_d6, eventout - - - h3 61 m9 71 82 k8 vss s - - - - - - j5 62 n9 72 83 l9 vdd s - - - - 40 g6 j4 63 r9 73 84 r9 pe10 i/o ft - tim1_ch2n, uart7_cts, quadspi_bk2_io3, fmc_d7, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 62/228 docid027589 rev 4 41 h6 k4 64 p10 74 85 p10 pe11 i/o ft - tim1_ch2, spi4_nss, sai2_sd_b, fmc_d8, lcd_g3, eventout - 42 j6 l4 65 r10 75 86 r10 pe12 i/o ft - tim1_ch3n, spi4_sck, sai2_sck_b, fmc_d9, lcd_b4, eventout - 43 k6 n4 66 n11 76 87 r12 pe13 i/o ft - tim1_ch3, spi4_miso, sai2_fs_b, fmc_d10, lcd_de, eventout - 44 g7 m4 67 p11 77 88 p11 pe14 i/o ft - tim1_ch4, spi4_mosi, sai2_mck_b, fmc_d11, lcd_clk, eventout - 45 h7 l3 68 r11 78 89 r11 pe15 i/o ft - tim1_bkin, fmc_d12, lcd_r7, eventout - 46 j7 m3 69 r12 79 90 p12 pb10 i/o ft - tim2_ch3, i2c2_scl, spi2_sck/i2s2_ck, usart3_tx, otg_hs_ulpi_d3, eth_mii_rx_er, lcd_g4, eventout - 47 k7 n3 70 r13 80 91 r13 pb11 i/o ft - tim2_ch4, i2c2_sda, usart3_rx, otg_hs_ulpi_d4, eth_mii_tx_en/eth_r mii_tx_en, lcd_g5, eventout - 48 f8 n2 71 m10 81 92 l11 vcap_1 s - - - - 49 - h2 - - - 93 k9 vss s - - - - 50 - j6 72 n10 82 94 l10 vdd s - - - - - - - - - - 95 m14 pj5 i/o ft - lcd_r6, eventout - -- --m118396p13ph6i/oft- i2c2_smba, spi5_sck, tim12_ch1, eth_mii_rxd2, fmc_sdne1, dcmi_d8, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 63/228 stm32f756xx pinouts and pin description 89 -- --n128497n13ph7i/oft- i2c3_scl, spi5_miso, eth_mii_rxd3, fmc_sdcke1, dcmi_d9, eventout - -- --m128598p14ph8i/oft- i2c3_sda, fmc_d16, dcmi_hsync, lcd_r2, eventout - -- --m138699n14ph9i/oft- i2c3_smba, tim12_ch2, fmc_d17, dcmi_d0, lcd_r3, eventout - - - - - l13 87 100 p15 ph10 i/o ft - tim5_ch1, i2c4_smba, fmc_d18, dcmi_d1, lcd_r4, eventout - - - - - l12 88 101 n15 ph11 i/o ft - tim5_ch2, i2c4_scl, fmc_d19, dcmi_d2, lcd_r5, eventout - - - - - k12 89 102 m15 ph12 i/o ft - tim5_ch3, i2c4_sda, fmc_d20, dcmi_d3, lcd_r6, eventout - - - - - h12 90 - k10 vss s - - - - - - - - j12 91 103 k11 vdd s - - - - 51 k8 m2 73 p12 92 104 l13 pb12 i/o ft - tim1_bkin, i2c2_smba, spi2_nss/i2s2_ws, usart3_ck, can2_rx, otg_hs_ulpi_d5, eth_mii_txd0/eth_rm ii_txd0, otg_hs_id, eventout - 52 j8 n1 74 p13 93 105 k14 pb13 i/o ft - tim1_ch1n, spi2_sck/i2s2_ck, usart3_cts, can2_tx, otg_hs_ulpi_d6, eth_mii_txd1/eth_rm ii_txd1, eventout otg_hs_vb us table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 64/228 docid027589 rev 4 53 h10 k3 75 r14 94 106 r14 pb14 i/o ft - tim1_ch2n, tim8_ch2n, spi2_miso, usart3_rts, tim12_ch1, otg_hs_dm, eventout - 54 g10 j3 76 r15 95 107 r15 pb15 i/o ft - rtc_refin, tim1_ch3n, tim8_ch3n, spi2_mosi/i2s2_sd, tim12_ch2, otg_hs_dp, eventout - 55 k9 l2 77 p15 96 108 l15 pd8 i/o ft - usart3_tx, spdifrx_in11, fmc_d13, eventout - 56 j9 m1 78 p14 97 109 l14 pd9 i/o ft - usart3_rx, fmc_d14, eventout - 57 h9 h4 79 n15 98 110 k15 pd10 i/o ft - usart3_ck, fmc_d15, lcd_b3, eventout - 58 g9 k2 80 n14 99 111 n10 pd11 i/o ft - i2c4_smba, usart3_cts, quadspi_bk1_io0, sai2_sd_a, fmc_a16/fmc_cle, eventout - 59 k10 h6 81 n13 100 112 m10 pd12 i/o ft - tim4_ch1, lptim1_in1, i2c4_scl, usart3_rts, quadspi_bk1_io1, sai2_fs_a, fmc_a17/fmc_ale, eventout - 60 j10 h5 82 m15 101 113 m11 pd13 i/o ft - tim4_ch2, lptim1_out, i2c4_sda, quadspi_bk1_io3, sai2_sck_a, fmc_a18, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 65/228 stm32f756xx pinouts and pin description 89 - - - 83 - 102 114 j10 vss s - - - - - - l1 84 j13 103 115 j11 vdd s - - - - 61 h8 j2 85 m14 104 116 l12 pd14 i/o ft - tim4_ch3, uart8_cts, fmc_d0, eventout - 62 g8 k1 86 l14 105 117 k13 pd15 i/o ft - tim4_ch4, uart8_rts, fmc_d1, eventout - - - - - - - 118 k12 pj6 i/o ft - lcd_r7, eventout - - - - - - - 119 j12 pj7 i/o ft - lcd_g0, eventout - - - - - - - 120 h12 pj8 i/o ft - lcd_g1, eventout - - - - - - - 121 j13 pj9 i/o ft - lcd_g2, eventout - - - - - - - 122 h13 pj10 i/o ft - lcd_g3, eventout - - - - - - - 123 g12 pj11 i/o ft - lcd_g4, eventout - - - - - - - 124 h11 vdd s - - - - - - - - - - 125 h10 vss s - - - - - - - - - - 126 g13 pk0 i/o ft - lcd_g5, eventout - - - - - - - 127 f12 pk1 i/o ft - lcd_g6, eventout - - - - - - - 128 f13 pk2 i/o ft - lcd_g7, eventout - - - j1 87 l15 106 129 m13 pg2 i/o ft - fmc_a12, eventout - - - g3 88 k15 107 130 m12 pg3 i/o ft - fmc_a13, eventout - - - g5 89 k14 108 131 n12 pg4 i/o ft - fmc_a14/fmc_ba0, eventout - - - g6 90 k13 109 132 n11 pg5 i/o ft - fmc_a15/fmc_ba1, eventout - - - g4 91 j15 110 133 j15 pg6 i/o ft - dcmi_d12, lcd_r7, eventout - - - h1 92 j14 111 134 j14 pg7 i/o ft - usart6_ck, fmc_int, dcmi_d13, lcd_clk, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 66/228 docid027589 rev 4 - - g2 93 h14 112 135 h14 pg8 i/o ft - spi6_nss, spdifrx_in2, usart6_rts, eth_pps_out, fmc_sdclk, eventout - - - d2 94 g12 113 136 g10 vss s - - - - - f6 g1 95 h13 114 137 g11 vddusb s - - - - 63 f10 f2 96 h15 115 138 h15 pc6 i/o ft - tim3_ch1, tim8_ch1, i2s2_mck, usart6_tx, sdmmc1_d6, dcmi_d0, lcd_hsync, eventout - 64 e10 f3 97 g15 116 139 g15 pc7 i/o ft - tim3_ch2, tim8_ch2, i2s3_mck, usart6_rx, sdmmc1_d7, dcmi_d1, lcd_g6, eventout - 65 f9 e4 98 g14 117 140 g14 pc8 i/o ft - traced1, tim3_ch3, tim8_ch3, uart5_rts, usart6_ck, sdmmc1_d0, dcmi_d2, eventout - 66 e9 e3 99 f14 118 141 f14 pc9 i/o ft - mco2, tim3_ch4, tim8_ch4, i2c3_sda, i2s_ckin, uart5_cts, quadspi_bk1_io0, sdmmc1_d1, dcmi_d3, eventout - 67 d9 f1 100 f15 119 142 f15 pa8 i/o ft - mco1, tim1_ch1, tim8_bkin2, i2c3_scl, usart1_ck, otg_fs_sof, lcd_r6, eventout - 68 c9 e2 101 e15 120 143 e15 pa9 i/o ft - tim1_ch2, i2c3_smba, spi2_sck/i2s2_ck, usart1_tx, dcmi_d0, eventout otg_fs_vb us table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 67/228 stm32f756xx pinouts and pin description 89 69 d10 d5 102 d15 121 144 d15 pa10 i/o ft - tim1_ch3, usart1_rx, otg_fs_id, dcmi_d1, eventout - 70 c10 d4 103 c15 122 145 c15 pa11 i/o ft - tim1_ch4, usart1_cts, can1_rx, otg_fs_dm, lcd_r4, eventout - 71 b10 e1 104 b15 123 146 b15 pa12 i/o ft - tim1_etr, usart1_rts, sai2_fs_b, can1_tx, otg_fs_dp, lcd_r5, eventout - 72 a10 d3 105 a15 124 147 a15 pa13(jt ms- swdio) i/o ft - jtms-swdio, eventout - 73 e7 d1 106 f13 125 148 e11 vcap_2 s - - - - 74 e5 d2 107 f12 126 149 f10 vss s - - - - 75 f5 c1 108 g13 127 150 f11 vdd s - - - - - - - - e12 128 151 e12 ph13 i/o ft - tim8_ch1n, can1_tx, fmc_d21, lcd_g2, eventout - - - - - e13 129 152 e13 ph14 i/o ft - tim8_ch2n, fmc_d22, dcmi_d4, lcd_g3, eventout - - - - - d13 130 153 d13 ph15 i/o ft - tim8_ch3n, fmc_d23, dcmi_d11, lcd_g4, eventout - - - - - e14 131 154 e14 pi0 i/o ft - tim5_ch4, spi2_nss/i2s2_ws, fmc_d24, dcmi_d13, lcd_g5, eventout - - - - - d14 132 155 d14 pi1 i/o ft - tim8_bkin2, spi2_sck/i2s2_ck, fmc_d25, dcmi_d8, lcd_g6, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 68/228 docid027589 rev 4 - - - - c14 133 156 c14 pi2 i/o ft - tim8_ch4, spi2_miso, fmc_d26, dcmi_d9, lcd_g7, eventout - - - - - c13 134 157 c13 pi3 i/o ft - tim8_etr, spi2_mosi/i2s2_sd, fmc_d27, dcmi_d10, eventout - - - f5 - d9 135 - f9 vss s - - - - - - a1 - c9 136 158 e10 vdd s - - - - 76 a9 b1 109 a14 137 159 a14 pa14(jt ck- swclk) i/o ft - jtck-swclk, eventout - 77 a8 c2 110 a13 138 160 a13 pa15(jt di) i/o ft - jtdi, tim2_ch1/tim2_etr, hdmi-cec, spi1_nss/i2s1_ws, spi3_nss/i2s3_ws, uart4_rts, eventout - 78 b9 a2 111 b14 139 161 b14 pc10 i/o ft - spi3_sck/i2s3_ck, usart3_tx, uart4_tx, quadspi_bk1_io1, sdmmc1_d2, dcmi_d8, lcd_r2, eventout - 79 b8 b2 112 b13 140 162 b13 pc11 i/o ft - spi3_miso, usart3_rx, uart4_rx, quadspi_bk2_ncs, sdmmc1_d3, dcmi_d4, eventout - 80 c8 c3 113 a12 141 163 a12 pc12 i/o ft - traced3, spi3_mosi/i2s3_sd, usart3_ck, uart5_tx, sdmmc1_ck, dcmi_d9, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 69/228 stm32f756xx pinouts and pin description 89 81 d8 b3 114 b12 142 164 b12 pd0 i/o ft - can1_rx, fmc_d2, eventout - 82 e8 c4 115 c12 143 165 c12 pd1 i/o ft - can1_tx, fmc_d3, eventout - 83 b7 a3 116 d12 144 166 d12 pd2 i/o ft - traced2, tim3_etr, uart5_rx, sdmmc1_cmd, dcmi_d11, eventout - 84 c7 b4 117 d11 145 167 c11 pd3 i/o ft - spi2_sck/i2s2_ck, usart2_cts, fmc_clk, dcmi_d5, lcd_g7, eventout - 85 d7 b5 118 d10 146 168 d11 pd4 i/o ft - usart2_rts, fmc_noe, eventout - 86 b6 a4 119 c11 147 169 c10 pd5 i/o ft - usart2_tx, fmc_nwe, eventout - - - - 120 d8 148 170 f8 vss s - - - - - - c5 121 c8 149 171 e9 vdd s - - - - 87 c6 f4 122 b11 150 172 b11 pd6 i/o ft - spi3_mosi/i2s3_sd, sai1_sd_a, usart2_rx, fmc_nwait, dcmi_d10, lcd_b2, eventout - 88 d6 a5 123 a11 151 173 a11 pd7 i/o ft - usart2_ck, spdifrx_in0, fmc_ne1, eventout - - - - - - - 174 b10 pj12 i/o ft - lcd_b0, eventout - - - - - - - 175 b9 pj13 i/o ft - lcd_b1, eventout - - - - - - - 176 c9 pj14 i/o ft - lcd_b2, eventout - - - - - - - 177 d10 pj15 i/o ft - lcd_b3, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 70/228 docid027589 rev 4 - - e5 124 c10 152 178 d9 pg9 i/o ft - spdifrx_in3, usart6_rx, quadspi_bk2_io2, sai2_fs_b, fmc_ne2/fmc_nce, dcmi_vsync, eventout - - - c6 125 b10 153 179 c8 pg10 i/o ft - lcd_g3, sai2_sd_b, fmc_ne3, dcmi_d2, lcd_b2, eventout - - -- b6 126 b9 154 180 b8 pg11 i/o ft - spdifrx_in0, eth_mii_tx_en/eth_r mii_tx_en, dcmi_d3, lcd_b3, eventout - - - a6 127 b8 155 181 c7 pg12 i/o ft - lptim1_in1, spi6_miso, spdifrx_in1, usart6_rts, lcd_b4, fmc_ne4, lcd_b1, eventout - - - d6 128 a8 156 182 b3 pg13 i/o ft - traced0, lptim1_out, spi6_sck, usart6_cts, eth_mii_txd0/eth_rm ii_txd0, fmc_a24, lcd_r0, eventout - - - f6 129 a7 157 183 a4 pg14 i/o ft - traced1, lptim1_etr, spi6_mosi, usart6_tx, quadspi_bk2_io3, eth_mii_txd1/eth_rm ii_txd1, fmc_a25, lcd_b0, eventout - - - - 130 d7 158 184 f7 vss s - - - - - - e6 131 c7 159 185 e8 vdd s - - - - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 71/228 stm32f756xx pinouts and pin description 89 - - - - - - 186 d8 pk3 i/o ft - lcd_b4, eventout - - - - - - - 187 d7 pk4 i/o ft - lcd_b5, eventout - - - - - - - 188 c6 pk5 i/o ft - lcd_b6, eventout - - - - - - - 189 c5 pk6 i/o ft - lcd_b7, eventout - - - - - - - 190 c4 pk7 i/o ft - lcd_de, eventout - - - a7 132 b7 160 191 b7 pg15 i/o ft - usart6_cts, fmc_sdncas, dcmi_d13, eventout - 89 a7 b7 133 a10 161 192 a10 pb3(jtd o/trac eswo) i/o ft - jtdo/traceswo, tim2_ch2, spi1_sck/i2s1_ck, spi3_sck/i2s3_ck, eventout - 90 a6 c7 134 a9 162 193 a9 pb4(njt rst) i/o ft - njtrst, tim3_ch1, spi1_miso, spi3_miso, spi2_nss/i2s2_ws, eventout - 91 c5 c8 135 a6 163 194 a8 pb5 i/o ft - tim3_ch2, i2c1_smba, spi1_mosi/i2s1_sd, spi3_mosi/i2s3_sd, can2_rx, otg_hs_ulpi_d7, eth_pps_out, fmc_sdcke1, dcmi_d10, eventout - 92 b5 a8 136 b6 164 195 b6 pb6 i/o ft - tim4_ch1, hdmi-cec, i2c1_scl, usart1_tx, can2_tx, quadspi_bk1_ncs, fmc_sdne1, dcmi_d5, eventout - 93 a5 b8 137 b5 165 196 b5 pb7 i/o ft - tim4_ch2, i2c1_sda, usart1_rx, fmc_nl, dcmi_vsync, eventout - 94 d5 c9 138 d6 166 197 e6 boot i b - - vpp table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 72/228 docid027589 rev 4 95 b4 a9 139 a5 167 198 a7 pb8 i/o ft - tim4_ch3, tim10_ch1, i2c1_scl, can1_rx, eth_mii_txd3, sdmmc1_d4, dcmi_d6, lcd_b6, eventout - 96 a4 b9 140 b4 168 199 b4 pb9 i/o ft - tim4_ch4, tim11_ch1, i2c1_sda, spi2_nss/i2s2_ws, can1_tx, sdmmc1_d5, dcmi_d7, lcd_b7, eventout - 97 d4 b10 141 a4 169 200 a6 pe0 i/o ft - tim4_etr, lptim1_etr, uart8_rx, sai2_mck_a, fmc_nbl0, dcmi_d2, eventout - 98 c4 a10 142 a3 170 201 a5 pe1 i/o ft - lptim1_in2, uart8_tx, fmc_nbl1, dcmi_d3, eventout - 99 e4 - - d5 - 202 f6 vss s - - - - - f7 a11 143 c6 171 203 e5 pdr_on s - - - - 100 f4 d7 144 c5 172 204 e7 vdd s - - - - - - - - d4 173 205 c3 pi4 i/o ft - tim8_bkin, sai2_mck_a, fmc_nbl2, dcmi_d5, lcd_b4, eventout - - - - - c4 174 206 d3 pi5 i/o ft - tim8_ch1, sai2_sck_a, fmc_nbl3, dcmi_vsync, lcd_b5, eventout - table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
docid027589 rev 4 73/228 stm32f756xx pinouts and pin description 89 - - - - c3 175 207 d6 pi6 i/o ft - tim8_ch2, sai2_sd_a, fmc_d28, dcmi_d6, lcd_b6, eventout - - - - - c2 176 208 d4 pi7 i/o ft - tim8_ch3, sai2_fs_a, fmc_d29, dcmi_d7, lcd_b7, eventout - 1. function availability depends on the chosen device. 2. pc13, pc14, pc15 and pi8 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 and pi8 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these i/os must not be used as a current source (e.g. to drive an led). 3. main function after the first backup domain power-up. later on, it depends on the contents of the rtc registers even after reset (because these registers are not reset by the main rese t). for details on how to manage these i/os, refer to the rtc register description sections in the st m32f75xxx and stm32f74xxx reference manual. 4. ft = 5 v tolerant except when in analog mode or oscillator mode (for pc14, pc15, ph0 and ph1). 5. if the device is delivered in an wlcsp143, uf bga176, lqfp176, tfbga100 or tfbga216 package, and the bypass_reg pin is set to v dd (regulator off/internal reset on mode), then pa0 is used as an internal reset (active low). table 10. stm32f756xx pin and ball definition (continued) pin number pin name (function after reset) (1) pin type i/o structure notes alternate functions additional functions lqfp100 tfbga100 wlcsp143 lqfp144 ufbga176 lqfp176 lqfp208 tfbga216
pinouts and pin description stm32f756xx 74/228 docid027589 rev 4 table 11. fmc pin definition pin name nor/psram/sr am nor/psram mux nand16 sdram pf0 a0 - - a0 pf1 a1 - - a1 pf2 a2 - - a2 pf3 a3 - - a3 pf4 a4 - - a4 pf5 a5 - - a5 pf12 a6 - - a6 pf13 a7 - - a7 pf14 a8 - - a8 pf15 a9 - - a9 pg0 a10 - - a10 pg1 a11 - - a11 pg2 a12 - - a12 pg3 a13 - - - pg4 a14 - - ba0 pg5 a15 - - ba1 pd11 a16 a16 cle - pd12 a17 a17 ale - pd13 a18 a18 - - pe3 a19 a19 - - pe4 a20 a20 - - pe5 a21 a21 - - pe6 a22 a22 - - pe2 a23 a23 - - pg13 a24 a24 - - pg14 a25 a25 - - pd14 d0 da0 d0 d0 pd15 d1 da1 d1 d1 pd0 d2 da2 d2 d2 pd1 d3 da3 d3 d3 pe7 d4 da4 d4 d4 pe8 d5 da5 d5 d5 pe9 d6 da6 d6 d6 pe10 d7 da7 d7 d7
docid027589 rev 4 75/228 stm32f756xx pinouts and pin description 89 pe11 d8 da8 d8 d8 pe12 d9 da9 d9 d9 pe13 d10 da10 d10 d10 pe14 d11 da11 d11 d11 pe15 d12 da12 d12 d12 pd8 d13 da13 d13 d13 pd9 d14 da14 d14 d14 pd10 d15 da15 d15 d15 ph8 d16 - - d16 ph9 d17 - - d17 ph10 d18 - - d18 ph11 d19 - - d19 ph12 d20 - - d20 ph13 d21 - - d21 ph14 d22 - - d22 ph15 d23 - - d23 pi0 d24 - - d24 pi1 d25 - - d25 pi2 d26 - - d26 pi3 d27 - - d27 pi6 d28 - - d28 pi7 d29 - - d29 pi9 d30 - - d30 pi10 d31 - - d31 pd7 ne1 ne1 - - pg9 ne2 ne2 nce - pg10 ne3 ne3 - - pg11---- pg12 ne4 ne4 - - pd3 clk clk - - pd4 noe noe noe - pd5 nwe nwe nwe - pd6 nwait nwait nwait - pb7 nadv nadv - - table 11. fmc pin definition (continued) pin name nor/psram/sr am nor/psram mux nand16 sdram
pinouts and pin description stm32f756xx 76/228 docid027589 rev 4 pf6 - - - - pf7 - - - - pf8 - - - - pf9 - - - - pf10---- pg6 - - - - pg7 - - int - pe0 nbl0 nbl0 - nbl0 pe1 nbl1 nbl1 - nbl1 pi4 nbl2 - - nbl2 pi5 nbl3 - - nbl3 pg8 - - - sdclk pc0 - - - sdnwe pf11 - - - sdnras pg15 - - - sdncas ph2 - - - sdcke0 ph3 - - - sdne0 ph6 - - - sdne1 ph7 - - - sdcke1 ph5 - - - sdnwe pc2 - - - sdne0 pc3 - - - sdcke0 pb5 - - - sdcke1 pb6 - - - sdne1 table 11. fmc pin definition (continued) pin name nor/psram/sr am nor/psram mux nand16 sdram
stm32f756xx pinouts and pin description docid027589 rev 4 77/228 table 12. stm32f756xx alternate function mapping port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys port a pa0 - tim2_c h1/tim2 _etr tim5_c h1 tim8_et r --- usart2 _cts uart4_ tx - sai2_sd_ b eth_mii_ crs --- even tout pa1 - tim2_c h2 tim5_c h2 ---- usart2 _rts uart4_ rx quadsp i_bk1_io 3 sai2_mc k_b eth_mii_ rx_clk/ eth_rmi i_ref_c lk - - lcd_r2 even tout pa2 - tim2_c h3 tim5_c h3 tim9_ch 1 --- usart2 _tx sai2_sc k_b -- eth_mdi o - - lcd_r1 even tout pa3 - tim2_c h4 tim5_c h4 tim9_ch 2 --- usart2 _rx -- otg_hs_ ulpi_d0 eth_mii_ col --lcd_b5 even tout pa4 - - - - - spi1_ns s/i2s1_ ws spi3_ns s/i2s3_ ws usart2 _ck -- - - otg_hs _sof dcmi_h sync lcd_vs ync even tout pa5 - tim2_c h1/tim2 _etr - tim8_ch 1n - spi1_sc k/i2s1_ ck ---- otg_hs_ ulpi_ck - - - lcd_r4 even tout pa6 - tim1_b kin tim3_c h1 tim8_bki n - spi1_mi so -- - tim13_c h1 --- dcmi_pi xclk lcd_g2 even tout pa7 - tim1_c h1n tim3_c h2 tim8_ch 1n - spi1_m osi/i2s1 _sd -- - tim14_c h1 - eth_mii_ rx_dv/e th_rmii_ crs_dv fmc_sd nwe -- even tout pa8 mco1 tim1_c h1 - tim8_bki n2 i2c3_sc l -- usart1 _ck -- otg_fs_ sof - - - lcd_r6 even tout pa9 - tim1_c h2 -- i2c3_sm ba spi2_sc k/i2s2_ ck - usart1 _tx -- - -- dcmi_d 0 - even tout pa10 - tim1_c h3 -- --- usart1 _rx -- otg_fs_ id -- dcmi_d 1 - even tout pa11 - tim1_c h4 -- --- usart1 _cts - can1_r x otg_fs_ dm - - - lcd_r4 even tout
pinouts and pin description stm32f756xx 78/228 docid027589 rev 4 port a pa12 - tim1_et r -- --- usart1 _rts sai2_fs _b can1_t x otg_fs_ dp - - - lcd_r5 even tout pa13 jtms- swdio -- - - -- - - - - - --- even tout pa14 jtck- swclk -- - - -- - - - - - --- even tout pa15 jtdi tim2_c h1/tim2 _etr -- hdmi- cec spi1_ns s/i2s1_ ws spi3_ns s/i2s3_ ws - uart4_ rts - - - --- even tout port b pb0 - tim1_c h2n tim3_c h3 tim8_ch 2n ---- uart4_ cts lcd_r3 otg_hs_ ulpi_d1 eth_mii_ rxd2 --- even tout pb1 - tim1_c h3n tim3_c h4 tim8_ch 3n - - - - - lcd_r6 otg_hs_ ulpi_d2 eth_mii_ rxd3 --- even tout pb2 - - - - - - sai1_sd _a spi3_mo si/i2s3_ sd quadsp i_clk - - --- even tout pb3 jtdo/t races wo tim2_c h2 -- - spi1_sc k/i2s1_ ck spi3_sc k/i2s3_ ck --- - ---- even tout pb4 njtrst - tim3_c h1 -- spi1_mi so spi3_mi so spi2_ns s/i2s2_ ws - - - - --- even tout pb5 - - tim3_c h2 - i2c1_sm ba spi1_m osi/i2s1 _sd spi3_m osi/i2s3 _sd -- can2_r x otg_hs_ ulpi_d7 eth_pps _out fmc_sd cke1 dcmi_d 10 - even tout pb6 - - tim4_c h1 hdmi- cec i2c1_sc l -- usart1 _tx - can2_t x quadspi _bk1_nc s - fmc_sd ne1 dcmi_d 5 - even tout pb7 - - tim4_c h2 - i2c1_sd a -- usart1 _rx - - - - fmc_nl dcmi_v sync - even tout pb8 - - tim4_c h3 tim10_c h1 i2c1_sc l -- - - can1_r x eth_mii_ txd3 sdmmc 1_d4 dcmi_d 6 lcd_b6 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid027589 rev 4 79/228 port b pb9 - - tim4_c h4 tim11_ch 1 i2c1_sd a spi2_ns s/i2s2_ ws -- - can1_t x -- sdmmc 1_d5 dcmi_d 7 lcd_b7 even tout pb10 - tim2_c h3 -- i2c2_sc l spi2_sc k/i2s2_ ck - usart3 _tx -- otg_hs_ ulpi_d3 eth_mii_ rx_er - - lcd_g4 even tout pb11 - tim2_c h4 -- i2c2_sd a -- usart3 _rx -- otg_hs_ ulpi_d4 eth_mii_ tx_en/e th_rmii_ tx_en - - lcd_g5 even tout pb12 - tim1_b kin -- i2c2_sm ba spi2_ns s/i2s2_ ws - usart3 _ck - can2_r x otg_hs_ ulpi_d5 eth_mii_ txd0/et h_rmii_t xd0 otg_hs _id -- even tout pb13 - tim1_c h1n -- - spi2_sc k/i2s2_ ck - usart3 _cts - can2_t x otg_hs_ ulpi_d6 eth_mii_ txd1/et h_rmii_t xd1 --- even tout pb14 - tim1_c h2n - tim8_ch 2n - spi2_mi so - usart3 _rts - tim12_c h1 -- otg_hs _dm -- even tout pb15 rtc_r efin tim1_c h3n - tim8_ch 3n - spi2_m osi/i2s2 _sd -- - tim12_c h2 -- otg_hs _dp -- even tout port c pc0--- - - -- - sai2_fs _b - otg_hs_ ulpi_st p - fmc_sd nwe - lcd_r5 even tout pc1 trace d0 -- - - spi2_m osi/i2s2 _sd sai1_sd _a --- - eth_md c --- even tout pc2 - - - - - spi2_mi so ---- otg_hs_ ulpi_dir eth_mii_ txd2 fmc_sd ne0 -- even tout pc3 - - - - - spi2_m osi/i2s2 _sd ---- otg_hs_ ulpi_nx t eth_mii_ tx_clk fmc_sd cke0 -- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 80/228 docid027589 rev 4 port c pc4 - - - - - i2s1_m ck -- spdifrx _in2 -- eth_mii_ rxd0/et h_rmii_ rxd0 fmc_sd ne0 -- even tout pc5--- - - -- - spdifrx _in3 -- eth_mii_ rxd1/et h_rmii_ rxd1 fmc_sd cke0 -- even tout pc6 - - tim3_c h1 tim8_ch 1 - i2s2_m ck -- usart6 _tx --- sdmmc 1_d6 dcmi_d 0 lcd_hs ync even tout pc7 - - tim3_c h2 tim8_ ch2 -- i2s3_m ck - usart6 _rx --- sdmmc 1_d7 dcmi_d 1 lcd_g6 even tout pc8 trace d1 - tim3_c h3 tim8_ ch3 --- uart5_ rts usart6 _ck --- sdmmc 1_d0 dcmi_d 2 - even tout pc9 mco2 - tim3_c h4 tim8_ ch4 i2c3_sd a i2s_cki n - uart5_ cts - quadsp i_bk1_io 0 -- sdmmc 1_d1 dcmi_d 3 - even tout pc10 - - - - - - spi3_sc k/i2s3_ ck usart3 _tx uart4_t x quadsp i_bk1_io 1 -- sdmmc 1_d2 dcmi_d 8 lcd_r2 even tout pc11 - - - - - - spi3_mi so usart3 _rx uart4_ rx quadsp i_bk2_n cs -- sdmmc 1_d3 dcmi_d 4 - even tout pc12 trace d3 -- - - - spi3_m osi/i2s3 _sd usart3 _ck uart5_t x --- sdmmc 1_ck dcmi_d 9 - even tout pc13---- ------ - ---- even tout pc14---- ------ - ---- even tout pc15---- ------ - ---- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid027589 rev 4 81/228 port d pd0--- - - -- - - can1_r x - - fmc_d2 - - even tout pd1--- - - -- - - can1_t x - - fmc_d3 - - even tout pd2 trace d2 - tim3_et r ----- uart5_ rx --- sdmmc 1_cmd dcmi_d 11 - even tout pd3 - - - - - spi2_sc k/i2s2_ ck - usart2 _cts -- - - fmc_cl k dcmi_d 5 lcd_g7 even tout pd4--- - - -- usart2 _rts -- - - fmc_n oe -- even tout pd5--- - - -- usart2 _tx -- - - fmc_n we -- even tout pd6 - - - - - spi3_m osi/i2s3 _sd sai1_sd _a usart2 _rx -- - - fmc_n wait dcmi_d 10 lcd_b2 even tout pd7--- - - -- usart2 _ck spdifrx _in0 --- fmc_ne 1 -- even tout pd8--- - - -- usart3 _tx spdifrx _in1 --- fmc_d1 3 -- even tout pd9--- - - -- usart3 _rx -- - - fmc_d1 4 -- even tout pd10 - - - - - - - usart3 _ck -- - - fmc_d1 5 -lcd_b3 even tout pd11 - - - - i2c4_sm ba -- usart3 _cts - quadsp i_bk1_io 0 sai2_sd_ a - fmc_a1 6/fmc_ cle -- even tout pd12 - - tim4_c h1 lptim1_i n1 i2c4_sc l -- usart3 _rts - quadsp i_bk1_io 1 sai2_fs_ a - fmc_a1 7/fmc_ ale -- even tout pd13 - - tim4_c h2 lptim1_ out i2c4_sd a -- - - quadsp i_bk1_io 3 sai2_sc k_a - fmc_a1 8 -- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 82/228 docid027589 rev 4 port d pd14 - - tim4_c h3 ----- uart8_ cts ---fmc_d0-- even tout pd15 - - tim4_c h4 ----- uart8_ rts ---fmc_d1-- even tout port e pe0 - - tim4_et r lptim1_e tr ---- uart8_ rx - sai2_mc k_a - fmc_nb l0 dcmi_d 2 - even tout pe1 - - - lptim1_i n2 ---- uart8_t x --- fmc_nb l1 dcmi_d 3 - even tout pe2 trace clk -- - - spi4_sc k sai1_m clk_a -- quadsp i_bk1_io 2 - eth_mii_ txd3 fmc_a2 3 -- even tout pe3 trace d0 -- - - - sai1_sd _b --- - - fmc_a1 9 -- even tout pe4 trace d1 -- - - spi4_ns s sai1_fs _a --- - - fmc_a2 0 dcmi_d 4 lcd_b0 even tout pe5 trace d2 -- tim9_ch 1 - spi4_mi so sai1_sc k_a --- - - fmc_a2 1 dcmi_d 6 lcd_g0 even tout pe6 trace d3 tim1_b kin2 - tim9_ch 2 - spi4_m osi sai1_sd _a --- sai2_mc k_b - fmc_a2 2 dcmi_d 7 lcd_g1 even tout pe7 - tim1_et r -- ---- uart7_ rx - quadspi _bk2_io0 -fmc_d4- - even tout pe8 - tim1_c h1n -- ---- uart7_t x - quadspi _bk2_io1 -fmc_d5- - even tout pe9 - tim1_c h1 -- ---- uart7_ rts - quadspi _bk2_io2 -fmc_d6- - even tout pe10 - tim1_c h2n -- ---- uart7_ cts - quadspi _bk2_io3 -fmc_d7- - even tout pe11 - tim1_c h2 -- - spi4_ns s ---- sai2_sd_ b - fmc_d8 - lcd_g3 even tout pe12 - tim1_c h3n -- - spi4_sc k ---- sai2_sc k_b -fmc_d9-lcd_b4 even tout pe13 - tim1_c h3 -- - spi4_mi so ---- sai2_fs_ b - fmc_d1 0 - lcd_de even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid027589 rev 4 83/228 port e pe14 - tim1_c h4 -- - spi4_m osi ---- sai2_mc k_b - fmc_d1 1 - lcd_cl k even tout pe15 - tim1_b kin -- ------ - - fmc_d1 2 - lcd_r7 even tout port f pf0 - - - - i2c2_sd a -- - - - - -fmc_a0-- even tout pf1 - - - - i2c2_sc l -- - - - - -fmc_a1-- even tout pf2 - - - - i2c2_sm ba -- - - - - -fmc_a2-- even tout pf3--- - - -- - - - - -fmc_a3-- even tout pf4--- - - -- - - - - -fmc_a4-- even tout pf5--- - - -- - - - - -fmc_a5-- even tout pf6 - - - tim10_c h1 - spi5_ns s sai1_sd _b - uart7_ rx quadsp i_bk1_io 3 - - --- even tout pf7 - - - tim11_ch 1 - spi5_sc k sai1_m clk_b - uart7_t x quadsp i_bk1_io 2 - - --- even tout pf8 - - - - - spi5_mi so sai1_sc k_b - uart7_ rts tim13_c h1 quadspi _bk1_io0 - --- even tout pf9 - - - - - spi5_m osi sai1_fs _b - uart7_ cts tim14_c h1 quadspi _bk1_io1 - --- even tout pf10---- ------ - -- dcmi_d 11 lcd_de even tout pf11 - - - - - spi5_m osi ---- sai2_sd_ b - fmc_sd nras dcmi_d 12 - even tout pf12---- ------ - -fmc_a6-- even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 84/228 docid027589 rev 4 port f pf13 - - - - i2c4_sm ba -- - - - - -fmc_a7-- even tout pf14 - - - - i2c4_sc l -- - - - - -fmc_a8-- even tout pf15 - - - - i2c4_sd a -- - - - - -fmc_a9-- even tout port g pg0--- - - -- - - - - - fmc_a1 0 -- even tout pg1--- - - -- - - - - - fmc_a1 1 -- even tout pg2--- - - -- - - - - - fmc_a1 2 -- even tout pg3--- - - -- - - - - - fmc_a1 3 -- even tout pg4--- - - -- - - - - - fmc_a1 4/fmc_ ba0 -- even tout pg5--- - - -- - - - - - fmc_a1 5/fmc_ ba1 -- even tout pg6--- - - -- - - - - - - dcmi_d 12 lcd_r7 even tout pg7--- - - -- - usart6 _ck --- fmc_in t dcmi_d 13 lcd_cl k even tout pg8 - - - - - spi6_ns s - spdifrx _in2 usart6 _rts -- eth_pps _out fmc_sd clk -- even tout pg9--- - - -- spdifrx _in3 usart6 _rx quadsp i_bk2_io 2 sai2_fs_ b - fmc_ne 2/fmc_ nce dcmi_v sync - even tout pg10 - - - - - - - - - lcd_g3 sai2_sd_ b - fmc_ne 3 dcmi_d 2 lcd_b2 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid027589 rev 4 85/228 port g pg11 - - - - - - - spdifrx _in0 -- - eth_mii_ tx_en/e th_rmii_ tx_en - dcmi_d 3 lcd_b3 even tout pg12 - - - lptim1_i n1 - spi6_mi so - spdifrx _in1 usart6 _rts lcd_b4 - - fmc_ne 4 -lcd_b1 even tout pg13 trace d0 -- lptim1_ out - spi6_sc k -- usart6 _cts -- eth_mii_ txd0/et h_rmii_t xd0 fmc_a2 4 - lcd_r0 even tout pg14 trace d1 -- lptim1_e tr - spi6_m osi -- usart6 _tx quadsp i_bk2_io 3 - eth_mii_ txd1/et h_rmii_t xd1 fmc_a2 5 -lcd_b0 even tout pg15 - - - - - - - - usart6 _cts --- fmc_sd ncas dcmi_d 13 - even tout port h ph0--- - - -- - - - - - --- even tout ph1--- - - -- - - - - - --- even tout ph2 - - - lptim1_i n2 ----- quadsp i_bk2_io 0 sai2_sc k_b eth_mii_ crs fmc_sd cke0 - lcd_r0 even tout ph3--- - - -- - - quadsp i_bk2_io 1 sai2_mc k_b eth_mii_ col fmc_sd ne0 - lcd_r1 even tout ph4 - - - - i2c2_sc l ----- otg_hs_ ulpi_nx t - --- even tout ph5 - - - - i2c2_sd a spi5_ns s ---- - - fmc_sd nwe -- even tout ph6 - - - - i2c2_sm ba spi5_sc k -- - tim12_c h1 - eth_mii_ rxd2 fmc_sd ne1 dcmi_d 8 - even tout ph7 - - - - i2c3_sc l spi5_mi so ---- - eth_mii_ rxd3 fmc_sd cke1 dcmi_d 9 - even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 86/228 docid027589 rev 4 port h ph8 - - - - i2c3_sd a ----- - - fmc_d1 6 dcmi_h sync lcd_r2 even tout ph9 - - - - i2c3_sm ba -- - - tim12_c h2 -- fmc_d1 7 dcmi_d 0 lcd_r3 even tout ph10 - - tim5_c h1 - i2c4_sm ba ----- - - fmc_d1 8 dcmi_d 1 lcd_r4 even tout ph11 - - tim5_c h2 - i2c4_sc l ----- - - fmc_d1 9 dcmi_d 2 lcd_r5 even tout ph12 - - tim5_c h3 - i2c4_sd a ----- - - fmc_d2 0 dcmi_d 3 lcd_r6 even tout ph13 - - - tim8_ch 1n ----- can1_t x -- fmc_d2 1 - lcd_g2 even tout ph14 - - - tim8_ch 2n ------ - - fmc_d2 2 dcmi_d 4 lcd_g3 even tout ph15 - - - tim8_ch 3n ------ - - fmc_d2 3 dcmi_d 11 lcd_g4 even tout port i pi0 - - tim5_c h4 -- spi2_ns s/i2s2_ ws ---- - - fmc_d2 4 dcmi_d 13 lcd_g5 even tout pi1 - - - tim8_bki n2 - spi2_sc k/i2s2_ ck ---- - - fmc_d2 5 dcmi_d 8 lcd_g6 even tout pi2 - - - tim8_ch 4 - spi2_mi so ---- - - fmc_d2 6 dcmi_d 9 lcd_g7 even tout pi3 - - - tim8_et r - spi2_m osi/i2s2 _sd ---- - - fmc_d2 7 dcmi_d 10 - even tout pi4 - - - tim8_bki n ------ sai2_mc k_a - fmc_nb l2 dcmi_d 5 lcd_b4 even tout pi5 - - - tim8_ch 1 ------ sai2_sc k_a - fmc_nb l3 dcmi_v sync lcd_b5 even tout pi6 - - - tim8_ch 2 ------ sai2_sd_ a - fmc_d2 8 dcmi_d 6 lcd_b6 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid027589 rev 4 87/228 port i pi7 - - - tim8_ch 3 ------ sai2_fs_ a - fmc_d2 9 dcmi_d 7 lcd_b7 even tout pi8--- - - -- - - - - - --- even tout pi9--- - - -- - - can1_r x -- fmc_d3 0 - lcd_vs ync even tout pi10---- ------ - eth_mii_ rx_er fmc_d3 1 - lcd_hs ync even tout pi11---- ------ otg_hs_ ulpi_dir - --- even tout pi12---- ------ - --- lcd_hs ync even tout pi13---- ------ - --- lcd_vs ync even tout pi14---- ------ - --- lcd_cl k even tout pi15 - - - - - - - - - - - - - - lcd_r0 even tout port j pj0--- - - -- - - - - - --lcd_r1 even tout pj1--- - - -- - - - - - --lcd_r2 even tout pj2--- - - -- - - - - - --lcd_r3 even tout pj3--- - - -- - - - - - --lcd_r4 even tout pj4--- - - -- - - - - - --lcd_r5 even tout pj5--- - - -- - - - - - --lcd_r6 even tout pj6--- - - -- - - - - - --lcd_r7 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
pinouts and pin description stm32f756xx 88/228 docid027589 rev 4 port j pj7--- - - -- - - - - - --lcd_g0 even tout pj8--- - - -- - - - - - --lcd_g1 even tout pj9--- - - -- - - - - - --lcd_g2 even tout pj10---- ------ - ---lcd_g3 even tout pj11---- ------ - ---lcd_g4 even tout pj12 - - - - - - - - - - - - - - lcd_b0 even tout pj13 - - - - - - - - - - - - - - lcd_b1 even tout pj14 - - - - - - - - - - - - - - lcd_b2 even tout pj15 - - - - - - - - - - - - - - lcd_b3 even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
stm32f756xx pinouts and pin description docid027589 rev 4 89/228 port k pk0--- - - -- - - - - - --lcd_g5 even tout pk1--- - - -- - - - - - --lcd_g6 even tout pk2--- - - -- - - - - - --lcd_g7 even tout pk3--- - - -- - - - - - --lcd_b4 even tout pk4--- - - -- - - - - - --lcd_b5 even tout pk5--- - - -- - - - - - --lcd_b6 even tout pk6--- - - -- - - - - - --lcd_b7 even tout pk7--- - - -- - - - - - --lcd_de even tout table 12. stm32f756xx alternate function mapping (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af13 af14 af15 sys tim1/2 tim3/4/5 tim8/9/10/ 11/lptim 1/cec i2c1/2/3/ 4/cec spi1/2/3/ 4/5/6 spi3/ sai1 spi2/3/u sart1/2/ 3/uart5/ spdifrx sai2/us art6/ua rt4/5/7/8 /spdifr x can1/2/t im12/13/ 14/quad spi/lcd sai2/qu adspi/o tg2_hs/ otg1_fs eth/ otg1_fs fmc/sd mmc1/o tg2_fs dcmi lcd sys
memory mapping stm32f756xx 90/228 docid027589 rev 4 4 memory mapping the memory map is shown in figure 19 . figure 19. memory map 069 0e\wh %orfn &ruwh[0 ,qwhuqdo shulskhudov 0e\wh %orfn )0& 0e\wh %orfn 4xdg63,dqg )0&edqn [ [))))))) [ [))))))) [ [))))))) [ [))))))) [ [))))))) [& [&))))))) [' ['))))))) [( [)))))))) 65$0.% 5hvhuyhg [[)))) [[%))) [[))))))) [ 5hvhuyhg [))) [[)))) [ 5hvhuyhg [&[))))))) $+% [['))))))) $+% '7&0.% [%)) [ 65$0.% [&[)))) $3% $3% [%)) [&[)))) 5hvhuyhg [[))))))) [)))) $+% 5hvhuyhg )odvkphpru\rq$;,0lqwhuidfh [)))[)))) [[))))) [[)))))) [[))) 5hvhuyhg 2swlrq%\whv 5hvhuyhg [)))[))))))) [ &ruwh[0lqwhuqdo shulskhudov [([())))) 5hvhuyhg [([)))))))) 0e\wh %orfn )0& 0e\wh %orfn )0&edqnwr edqn 0e\wh %orfn 3hulskhudov 0e\wh %orfn 65$0 0e\wh %orfn 5hvhuyhg [[))()))) )odvkphpru\rq,7&0lqwhuidfh [[))))) [[))))) [[))))) ,7&05$0 5hvhuyhg 6\vwhpphpru\ 5hvhuyhg [[('%)
docid027589 rev 4 91/228 stm32f756xx memory mapping 94 table 13. stm32f756xx register boundary addresses bus boundary address peripheral 0xe00f ffff - 0xffff ffff reserved cortex-m7 0xe000 0000 - 0xe00f ffff cortex-m7 internal peripherals ahb3 0xd000 0000 - 0xdfff ffff fmc bank 6 0xc000 0000 - 0xcfff ffff fmc bank 5 0xa000 2000 - 0xbfff ffff reserved 0xa000 1000 - 0xa000 1fff quad-spi control register 0xa000 0000- 0xa000 0fff fmc control register 0x9000 0000 - 0x9fff ffff quad-spi 0x8000 0000 - 0x8fff ffff fmc bank 3 0x7000 0000 - 0x7fff ffff fmc bank 2 0x6000 0000 - 0x6fff ffff fmc bank 1 0x5006 0c00- 0x5fff ffff reserved ahb2 0x5006 0800 - 0x5006 0bff rng 0x5006 0400 - 0x5006 07ff hash 0x5006 0000 - 0x5006 03ff cryp 0x5005 0400 - 0x5005 ffff reserved 0x5005 0000 - 0x5005 03ff dcmi 0x5004 0000- 0x5004 ffff reserved 0x5000 0000 - 0x5003 ffff usb otg fs
memory mapping stm32f756xx 92/228 docid027589 rev 4 0x4008 0000- 0x4fff ffff reserved ahb1 0x4004 0000 - 0x4007 ffff usb otg hs 0x4002 bc00- 0x4003 ffff reserved 0x4002 b000 - 0x4002 bbff chrom-art (dma2d) 0x4002 9400 - 0x4002 afff reserved 0x4002 9000 - 0x4002 93ff ethernet mac 0x4002 8c00 - 0x4002 8fff 0x4002 8800 - 0x4002 8bff 0x4002 8400 - 0x4002 87ff 0x4002 8000 - 0x4002 83ff 0x4002 6800 - 0x4002 7fff reserved 0x4002 6400 - 0x4002 67ff dma2 0x4002 6000 - 0x4002 63ff dma1 0x4002 5000 - 0x4002 5fff reserved 0x4002 4000 - 0x4002 4fff bkpsram 0x4002 3c00 - 0x4002 3fff flash interface register 0x4002 3800 - 0x4002 3bff rcc 0x4002 3400 - 0x4002 37ff reserved 0x4002 3000 - 0x4002 33ff crc 0x4002 2c00 - 0x4002 2fff reserved 0x4002 2800 - 0x4002 2bff gpiok 0x4002 2400 - 0x4002 27ff gpioj 0x4002 2000 - 0x4002 23ff gpioi 0x4002 1c00 - 0x4002 1fff gpioh 0x4002 1800 - 0x4002 1bff gpiog 0x4002 1400 - 0x4002 17ff gpiof 0x4002 1000 - 0x4002 13ff gpioe 0x4002 0c00 - 0x4002 0fff gpiod 0x4002 0800 - 0x4002 0bff gpioc 0x4002 0400 - 0x4002 07ff gpiob 0x4002 0000 - 0x4002 03ff gpioa table 13. stm32f756xx register boundary addresses (continued) bus boundary address peripheral
docid027589 rev 4 93/228 stm32f756xx memory mapping 94 0x4001 6c00- 0x4001 ffff reserved apb2 0x4001 6800 - 0x4001 6bff lcd-tft 0x4001 6000 - 0x4001 67ff reserved 0x4001 5c00 - 0x4001 5fff sai2 0x4001 5800 - 0x4001 5bff sai1 0x4001 5400 - 0x4001 57ff spi6 0x4001 5000 - 0x4001 53ff spi5 0x4001 4c00 - 0x4001 4fff reserved 0x4001 4800 - 0x4001 4bff tim11 0x4001 4400 - 0x4001 47ff tim10 0x4001 4000 - 0x4001 43ff tim9 0x4001 3c00 - 0x4001 3fff exti 0x4001 3800 - 0x4001 3bff syscfg 0x4001 3400 - 0x4001 37ff spi4 0x4001 3000 - 0x4001 33ff spi1/i2s1 0x4001 2c00 - 0x4001 2fff sdmmc 0x4001 2400 - 0x4001 2bff reserved 0x4001 2000 - 0x4001 23ff adc1 - adc2 - adc3 0x4001 1800 - 0x4001 1fff reserved 0x4001 1400 - 0x4001 17ff usart6 0x4001 1000 - 0x4001 13ff usart1 0x4001 0800 - 0x4001 0fff reserved 0x4001 0400 - 0x4001 07ff tim8 0x4001 0000 - 0x4001 03ff tim1 table 13. stm32f756xx register boundary addresses (continued) bus boundary address peripheral
memory mapping stm32f756xx 94/228 docid027589 rev 4 0x4000 8000- 0x4000 ffff reserved apb1 0x4000 7c00 - 0x4000 7fff uart8 0x4000 7800 - 0x4000 7bff uart7 0x4000 7400 - 0x4000 77ff dac 0x4000 7000 - 0x4000 73ff pwr 0x4000 6c00 - 0x4000 6fff hdmi-cec 0x4000 6800 - 0x4000 6bff can2 0x4000 6400 - 0x4000 67ff can1 0x4000 6000 - 0x4000 63ff i2c4 0x4000 5c00 - 0x4000 5fff i2c3 0x4000 5800 - 0x4000 5bff i2c2 0x4000 5400 - 0x4000 57ff i2c1 0x4000 5000 - 0x4000 53ff uart5 0x4000 4c00 - 0x4000 4fff uart4 0x4000 4800 - 0x4000 4bff usart3 0x4000 4400 - 0x4000 47ff usart2 0x4000 4000 - 0x4000 43ff spdifrx 0x4000 3c00 - 0x4000 3fff spi3 / i2s3 0x4000 3800 - 0x4000 3bff spi2 / i2s2 0x4000 3400 - 0x4000 37ff reserved 0x4000 3000 - 0x4000 33ff iwdg 0x4000 2c00 - 0x4000 2fff wwdg 0x4000 2800 - 0x4000 2bff rtc & bkp registers 0x4000 2400 - 0x4000 27ff lptim1 0x4000 2000 - 0x4000 23ff tim14 0x4000 1c00 - 0x4000 1fff tim13 0x4000 1800 - 0x4000 1bff tim12 0x4000 1400 - 0x4000 17ff tim7 0x4000 1000 - 0x4000 13ff tim6 0x4000 0c00 - 0x4000 0fff tim5 0x4000 0800 - 0x4000 0bff tim4 0x4000 0400 - 0x4000 07ff tim3 0x4000 0000 - 0x4000 03ff tim2 table 13. stm32f756xx register boundary addresses (continued) bus boundary address peripheral
docid027589 rev 4 95/228 stm32f756xx electrical characteristics 196 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 1.7 v v dd 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 20 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 21 . figure 20. pin loading conditions figure 21. pin input voltage -36 #p& -#5pin -36 -#5pin 6 ).
electrical characteristics stm32f756xx 96/228 docid027589 rev 4 5.1.6 power supply scheme figure 22. power supply scheme 1. to connect bypass_reg and pdr_on pins, refer to section 2.17: power supply supervisor and section 2.18: voltage regulator 2. the two 2.2 f ceramic capacitors should be replaced by tw o 100 nf decoupling capacitors when the voltage regulator is off. 3. the 4.7 f ceramic capacitor must be connected to one of the v dd pin. 4. v dda =v dd and v ssa =v ss . caution: each power supply pair (v dd /v ss , v dda /v ssa ...) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure good operation of the device. it is not recommended to remove filterin g capacitors to reduce pcb size or cost. this might cause incorrect operation of the device. 06y9 s l?lxxxel? vo}pw z?uw>>u xxx w}? ?]?z s d 'w /lk? khd /e <?voo}p] ~whu ]p]?o ?zd l?]?]??? ~k^??o?z](?? /k >}p] s =r& s z& v& =r& s &o?zuu}?? s wz s wz? ???x?r& zw^^zz' wzzke z?? }v??}oo? v& kd'&^ w,z v& s h^ =r& s h^
docid027589 rev 4 97/228 stm32f756xx electrical characteristics 196 5.1.7 current consumption measurement figure 23. current consum ption measurement scheme 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 14: voltage characteristics , table 15: current characteristics , and table 16: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. ai 6 "!4 6 $$ 6 $$! ) $$ ?6 "!4 ) $$ table 14. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda , v dd, v bat and v ddusb ) (1) 1. all main power (v dd , v dda , v ddusb ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ? 0.3 4.0 v v in input voltage on ft pins (2) 2. v in maximum value must always be respected. refer to table 15 for the values of the maximum allowed injected current. v ss ? 0.3 v dd +4.0 input voltage on tta pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 input voltage on boot pin v ss 9.0 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins (3) 3. include vref- pin. -50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.15: absolute maximum ratings (electrical sensitivity) -
electrical characteristics stm32f756xx 98/228 docid027589 rev 4 table 15. current characteristics symbol ratings max. unit i vdd total current into sum of all v dd_x power lines (source) (1) 320 ma i vss total current out of sum of all v ss_x ground lines (sink) (1) ? 320 i vddusb total current into v ddusb power line (source) 25 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss_x ground line (sink) (1) ? 100 i io output current sunk by any i/o and control pin 25 output current sourced by any i/os and control pin ? 25 i io total output current sunk by sum of all i/o and control pins (2) 120 total output current sunk by sum of all usb i/os 25 total output current sourced by sum of all i/os and control pins (2) ? 120 i inj(pin) injected current on ft, ftf, rst and b pins (3) ? 5/+0 injected current on tta pins (4) 5 i inj(pin) (4) total injected current (sum of all i/o and control pins) (5) 25 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to t he external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the to tal output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in >v dda while a negative inject ion is induced by v in docid027589 rev 4 99/228 stm32f756xx electrical characteristics 196 5.3 operating conditions 5.3.1 general operating conditions table 17. general operating conditions symbol parameter conditions (1) min typ max unit f hclk internal ahb clock frequency power scale 3 (vos[1:0] bits in pwr_cr register = 0x01), regulator on, over-drive off 0 - 144 mhz power scale 2 (vos[1:0] bits in pwr_cr register = 0x10), regulator on over- drive off 0 -168 over- drive on -180 power scale 1 (vos[1:0] bits in pwr_cr register= 0x11), regulator on over- drive off 0 -180 over- drive on - 216 (2) f pclk1 internal apb1 clock frequency over-drive off 0 - 45 over-drive on 0 - 54 f pclk2 internal apb2 clock frequency over-drive off 0 - 90 over-drive on 0 - 108 v dd standard operating voltage - 1.7 (3) -3.6 v v dda (4) (5) analog operating voltage (adc limited to 1.2 m samples) must be the same potential as v dd (6) 1.7 (3) -2.4 analog operating voltage (adc limited to 2.4 m samples) 2.4 - 3.6 v ddusb usb supply voltage (supply voltage for pa11,pa12, pb14 and pb15 pins) usb not used 1.7 3.3 3.6 usb used 3.0 - 3.6 v bat backup operating voltage - 1.65 - 3.6
electrical characteristics stm32f756xx 100/228 docid027589 rev 4 v 12 regulator on: 1.2 v internal voltage on v cap_1 /v cap_2 pins power scale 3 ((vos[1:0] bits in pwr_cr register = 0x01), 144 mhz hclk max frequency 1.08 1.14 1.20 v power scale 2 ((vos[1:0] bits in pwr_cr register = 0x10), 168 mhz hclk max frequency with over-drive off or 180 mhz with over-drive on 1.20 1.26 1.32 power scale 1 ((vos[1:0] bits in pwr_cr register = 0x11), 180 mhz hclk max frequency with over-drive off or 216 mhz with over-drive on 1.26 1.32 1.40 regulator off: 1.2 v external voltage must be supplied from external regulator on v cap_1 /v cap_2 pins (7) max frequency 144 mhz 1.10 1.14 1.20 max frequency 168mhz 1.20 1.26 1.32 max frequency 180 mhz 1.26 1.32 1.38 v in input voltage on rst and ft pins (8) 2 v v dd 3.6 v ? 0.3 - 5.5 v dd 2 v ? 0.3 - 5.2 input voltage on tta pins - ? 0.3 - v dda + 0.3 input voltage on boot pin - 0 - 9 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (9) lqfp100 - - 465 mw tfbga100 - - 351 wlcsp143 - - 641 lqfp144 - - 500 lqfp176 - - 526 ufbga176 - - 513 lqfp208 - - 1053 tfbga216 - - 690 t a ambient temperature for 6 suffix version maximum power dissipation ? 40 - 85 c low power dissipation (10) ? 40 - 105 ambient temperature for 7 suffix version maximum power dissipation ? 40 - 105 c low power dissipation (10) ? 40 - 125 t j junction temperature range 6 suffix version ? 40 - 105 c 7 suffix version ? 40 - 125 1. the over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 v. 2. 216 mhz maximum frequency for 6 suffix version (200 mhz maximum frequency for 7 suffix version). 3. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 2.17.2: internal reset off ). 4. when the adc is used, refer to table 62: adc characteristics . 5. if v ref+ pin is present, it must res pect the following condition: v dda -v ref+ < 1.2 v. table 17. general operating conditions (continued) symbol parameter conditions (1) min typ max unit
docid027589 rev 4 101/228 stm32f756xx electrical characteristics 196 5.3.2 vcap1/vcap2 external capacitor stabilization for the main regula tor is achieved by connecting an external capacitor c ext to the vcap1/vcap2 pins. c ext is specified in table 19 . figure 24. external capacitor c ext 1. legend: esr is the equivalent series resistance. 6. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and power-down operation. 7. the over-drive mode is not supported when the internal regulator is off. 8. to sustain a voltage higher than vdd+0.3, the internal pull-up and pull-down re sistors must be disabled 9. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax . 10. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax . table 18. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum hclk frequency vs flash memory wait states (1)(2) i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) conversion time up to 1.2 msps 20 mhz 180 mhz with 8 wait states and over-drive off no i/o compensation 8-bit erase and program operations only v dd = 2.1 to 2.4 v conversion time up to 1.2 msps 22 mhz 216 mhz with 9 wait states and over-drive on no i/o compensation 16-bit erase and program operations v dd = 2.4 to 2.7 v conversion time up to 2.4 msps 24 mhz 216 mhz with 8 wait states and over-drive on i/o compensation works 16-bit erase and program operations v dd = 2.7 to 3.6 v (4) conversion time up to 2.4 msps 30 mhz 216 mhz with 7 wait states and over-drive on i/o compensation works 32-bit erase and program operations 1. applicable only when the code is executed from flash memory. when the code is executed from ram, no wait state is required. 2. thanks to the art accelerator on itcm interface and l1-cache on axi interface, the number of wait states given here does not impact the execution speed from flash memory si nce the art accelerator or l1 -cache allows to achieve a performance equivalent to 0-wait state program execution. 3. v dd /v dda minimum value of 1.7 v is obtained with the use of an external power supply supervisor (refer to section 2.17.2: internal reset off ). 4. the voltage range for usb full speed phys can drop down to 2. 7 v. however the electrical characteristics of d- and d+ pins will be degraded between 2.7 and 3 v. 069 (65 5 /hdn &
electrical characteristics stm32f756xx 102/228 docid027589 rev 4 5.3.3 operating conditi ons at power-up / powe r-down (regulator on) subject to general operating conditions for t a . table 20. operating conditions at power-up / power-down (regulator on) 5.3.4 operating conditi ons at power-up / powe r-down (regulator off) subject to general operating conditions for t a . 5.3.5 reset and power cont rol block characteristics the parameters given in table 22 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . table 19. vcap1/vcap2 operating conditions (1) 1. when bypassing the voltage regulator, the two 2.2 f v cap capacitors are not required and should be replaced by two 100 nf decoupling capacitors. symbol parameter conditions cext capacitance of external capacitor 2.2 f esr esr of external capacitor < 2 symbol parameter min max unit t vdd v dd rise time rate 20 s/v v dd fall time rate 20 table 21. operating conditions at power-up / power-down (regulator off) (1) 1. to reset the internal logic at power-down, a reset must be applied on pin pa0 when v dd reach below 1.08 v. symbol parameter conditions min max unit t vdd v dd rise time rate power-up 20 s/v v dd fall time rate power-down 20 t vcap v cap_1 and v cap_2 rise time rate power-up 20 v cap_1 and v cap_2 fall time rate power-down 20
docid027589 rev 4 103/228 stm32f756xx electrical characteristics 196 table 22. reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.09 2.14 2.19 v pls[2:0]=000 (falling edge) 1.98 2.04 2.08 v pls[2:0]=001 (rising edge) 2.23 2.30 2.37 v pls[2:0]=001 (falling edge) 2.13 2.19 2.25 v pls[2:0]=010 (rising edge) 2.39 2.45 2.51 v pls[2:0]=010 (falling edge) 2.29 2.35 2.39 v pls[2:0]=011 (risi ng edge) 2.54 2.60 2.65 v pls[2:0]=011 (fallin g edge) 2.44 2.51 2.56 v pls[2:0]=100 (rising edge) 2.70 2.76 2.82 v pls[2:0]=100 (falling edge) 2.59 2.66 2.71 v pls[2:0]=101 (rising edge) 2.86 2.93 2.99 v pls[2:0]=101 (falling edge) 2.65 2.84 2.92 v pls[2:0]=110 (risi ng edge) 2.96 3.03 3.10 v pls[2:0]=110 (fallin g edge) 2.85 2.93 2.99 v pls[2:0]=111 (rising edge) 3.07 3.14 3.21 v pls[2:0]=111 (fallin g edge) 2.95 3.03 3.09 v v pvdhyst (1) pvd hysteresis - - 100 - mv v por/pdr power-on/power-down reset threshold falling edge 1.60 1.68 1.76 v rising edge 1.64 1.72 1.80 v v pdrhyst (1) pdr hysteresis - - 40 - mv v bor1 brownout level 1 threshold falling edge 2.13 2.19 2.24 v rising edge 2.23 2.29 2.33 v v bor2 brownout level 2 threshold falling edge 2.44 2.50 2.56 v rising edge 2.53 2.59 2.63 v v bor3 brownout level 3 threshold falling edge 2.75 2.83 2.88 v rising edge 2.85 2.92 2.97 v v borhyst (1) bor hysteresis - - 100 - mv t rsttempo (1)(2) por reset temporization - 0.5 1.5 3.0 ms i rush (1) inrush current on voltage regulator power- on (por or wakeup from standby) - - 160 250 ma e rush (1) inrush energy on voltage regulator power- on (por or wakeup from standby) v dd = 1.7 v, t a = 105 c, i rush = 171 ma for 31 s --5.4c
electrical characteristics stm32f756xx 104/228 docid027589 rev 4 5.3.6 over-drive switching characteristics when the over-drive mode switches from enabl ed to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. the over-drive switching c haracteristics are given in table 23 . they are sbject to general operating conditions for t a . 5.3.7 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 23: current consumption measurement scheme . all the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consum ption equivalent to coremark code. 1. guaranteed by design. 2. the reset temporization is measured from the power-on (por reset or wakeup from v bat ) to the instant when first instruction is read by the user application code. table 23. over-drive switching characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit tod_swen over_drive switch enable time hsi - 45 - s hse max for 4 mhz and min for 26 mhz 45 - 100 external hse 50 mhz - 40 - tod_swdis over_drive switch disable time hsi - 20 - hse max for 4 mhz and min for 26 mhz. 20 - 80 external hse 50 mhz - 15 -
docid027589 rev 4 105/228 stm32f756xx electrical characteristics 196 typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load). ? all peripherals are disabled except if it is explicitly mentioned. ? the flash memory access time is adjusted both to f hclk frequency and v dd range (see table 18: limitations depending on the operating power supply range ). ? when the regulator is on, the voltage scaling and over-drive mode are adjusted to f hclk frequency as follows: ? scale 3 for f hclk 144 mhz ? scale 2 for 144 mhz < f hclk 168 mhz ? scale 1 for 168 mhz < f hclk 216 mhz. the over-drive is only on at 216 mhz. ? when the regulator is off, the v12 is provided externally as described in table 17: general operating conditions : ? the system clock is hclk, f pclk1 = f hclk /4, and f pclk2 = f hclk /2. ? external clock frequency is 25 mhz and pll is on when f hclk is higher than 25 mhz. ? the typical current consumption values are obtained for 1.7 v v dd 3.6 v voltage range and for t a = 25 c unless otherwise specified. ? the maximum values are obtained for 1.7 v v dd 3.6 v voltage range and a maximum ambient temperature (t a ) unless otherwise specified. ? for the voltage range 1.7 v v dd 3.6 v, the maximum frequency is 180 mhz. table 24. typical and maximum current consumpt ion in run mode, code with data processing running from itcm ram, regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode all peripherals enabled (2)(3) 216 178 208 (4) 230 (4) - ma 200 165 193 212 230 180 147 171 (4) 185 (4) 198 (4) 168 130 152 164 177 144 100 116 127 137 60 44 52 63 73 25 21 25 36 46 all peripherals disabled (3) 216 102 120 (4) 141 (4) - 200 95 111 131 149 180 84 98 (4) 112 (4) 125 (4) 168 75 87 100 112 144 58 67 77 88 60 25 30 41 51 25 12 15 25 36 1. guaranteed by characterization results.
electrical characteristics stm32f756xx 106/228 docid027589 rev 4 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 register), add an additional pow er consumption of 1.73 ma per adc for the analog part. 4. guaranteed by test in production. table 25. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art on except prefetch / l1-cache on) or sram on axi (l1-cache on), regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in run mode all peripherals enabled (2)(3) 216 186 213 234 - ma 200 172 197 217 235 180 152 175 189 202 168 135 155 168 180 144 104 119 130 140 60 46 53 64 74 25 22 25 36 47 all peripherals disabled (3) 216 108 124 146 - 200 100 115 135 154 180 89 102 116 129 168 79 90 103 115 144 61 69 80 90 60 27 31 42 52 25 12 15 26 36 1. guaranteed by characterization results. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 register), add an additional pow er consumption of 1.73 ma per adc for the analog part.
docid027589 rev 4 107/228 stm32f756xx electrical characteristics 196 table 26. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory or sram on axi (l1-cache disabled), regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit ta= 25 c ta=85 c ta=105 c i dd supply current in run mode all peripherals enabled (2)(3) 216 181 210 233 - ma 200 168 194 216 234 180 153 176 192 206 168 136 157 172 184 144 109 125 137 148 60 53 61 73 84 25 26 30 41 52 all peripherals disabled (3) 216 105 121 145 - 200 98 112 134 153 180 90 103 119 132 168 81 93 107 120 144 67 76 88 89 60 34 40 51 62 25 17 20 31 42 1. guaranteed by characterization results. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.73 ma per adc for the analog part.
electrical characteristics stm32f756xx 108/228 docid027589 rev 4 table 27. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory on itcm interface (art disabled), regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit ta= 25 c ta=85 c ta=105 c i dd supply current in run mode all peripherals enabled (2)(3) 216 205 237 261 - ma 200 191 219 241 260 180 176 202 218 232 168 158 181 196 209 144 130 148 161 172 60 58 67 79 89 25 27 32 43 54 all peripherals disabled (3) 216 130 149 173 - 200 121 138 160 179 180 113 129 145 159 168 102 116 131 144 144 88 100 112 123 60 40 45 57 68 25 19 22 33 44 1. guaranteed by characterization results. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi ar e on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.73 ma per adc for the analog part.
docid027589 rev 4 109/228 stm32f756xx electrical characteristics 196 table 28. typical and maximum current consumpt ion in run mode, code with data processing running from flash memory (art on except prefetch / l1-cache on) or sram on axi (l1-cache on), regulator off symbol parameter conditions f hclk (mhz) typ max (1) unit ta= 25 c ta= 85 c ta= 105 c idd12 idd idd12 idd idd12 idd idd12 idd idd12/ idd supply current in run mode from v12 and vdd supply all peripherals enabled (2)(3) 180 151 1 174 2 190 2 204 2 ma 168 135 1 156 2 170 2 182 2 144 108 1 124 2 136 2 146 2 60 52 1 60 2 71 2 82 2 25 25 1 29 2 40 2 50 2 all peripherals disabled (3) 180 89 1 102 2 117 2 130 2 168 80 1 91 2 105 2 118 2 144 66 1 75 2 86 2 97 2 60 33 1 38 2 49 2 60 2 25 16 1 18 2 29 2 40 2 1. guaranteed by characterization results. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. when the adc is on (adon bit set in the adc_cr2 regist er), add an additional power consumption of 1.73 ma per adc for the analog part.
electrical characteristics stm32f756xx 110/228 docid027589 rev 4 table 29. typical and maximum current consumption in sleep mode, regulator on symbol parameter conditions f hclk (mhz) typ max (1) unit t a = 25 c t a = 85 c t a = 105 c i dd supply current in sleep mode all peripherals enabled (2) 216 116 137 (3) 159 (3) - ma 200 108 127 147 166 180 95 112 (3) 126 (3) 140 (3) 168 85 99 112 125 144 65 76 87 98 60 30 35 46 57 25 15 18 29 39 all peripherals disabled 216 35 46 (3) 71 (3) - 200 32 43 66 86 180 28 38 (3) 53 (3) 70 (3) 168 25 33 47 61 144 20 26 37 50 60 10 14 26 36 25 5 8 20 31 1. guaranteed by characterization results. 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. 3. guaranteed by test in production. table 30. typical and maximum current c onsumption in sleep mode, regulator off symbol parameter conditions f hclk (mhz) typ max (1) unit ta= 25 c ta= 85 c ta= 105 c idd12 idd idd12 idd idd12 idd idd12 idd idd12/ idd supply current in run mode from v12 and v dd supply all peripherals enabled (2) 180 94 1 110 2 125 2 138 2 ma 168 83 1 96 2 111 2 123 2 144 64 1 74 2 85 2 96 2 60 29 1 34 2 44 2 55 2 25 14 1 16 2 27 2 37 2 all peripherals disabled 180 27 1 36 2 51 2 68 2 168 24 1 31 2 45 2 59 2 144 18 1 24 2 35 2 48 2 60 9 1 12 2 24 2 34 2 25 4 1 6 2 18 2 29 2 1. guaranteed by characterization results.
docid027589 rev 4 111/228 stm32f756xx electrical characteristics 196 2. when analog peripheral blocks such as adcs, dacs, hse, lse, hsi, or lsi are on, an additional power consumption should be considered. table 31. typical and maximum current consumptions in stop mode symbol parameter conditions typ max (1) unit v dd = 3.6 v t a = 25 c t a = 25 c t a = 85 c t a = 105 c i dd_stop_nm (normal mode) supply current in stop mode, main regulator in run mode flash memory in stop mode, all oscillators off, no iwdg 0.45 2.00 14.00 22.00 ma flash memory in deep power down mode, all oscillators off 0.40 2.00 14.00 22.00 supply current in stop mode, main regulator in low-power mode flash memory in stop mode, all oscillators off, no iwdg 0.32 1.50 10.00 18.00 flash memory in deep power down mode, all oscillators off, no iwdg 0.27 1.50 10.00 18.00 i dd_stop_udm (under-drive mode) supply current in stop mode, main regulator in low voltage and under- drive modes regulator in run mode, flash memory in deep power down mode, all oscillators off, no iwdg 0.15 0.80 4.00 7.00 regulator in low-power mode, flash memory in deep power down mode, all oscillators off, no iwdg 0.10 0.70 4.00 7.00 1. data based on characterization, tested in production.
electrical characteristics stm32f756xx 112/228 docid027589 rev 4 table 32. typical and maximum current consumptions in standby mode symbol parameter conditions typ (1) max (2) unit t a = 25 c t a = 25 c t a = 85 c t a = 105 c v dd = 1.7 v v dd = 2.4 v v dd = 3.3 v v dd = 3.3 v i dd_stby supply current in standby mode backup sram off, rtc and lse off 1.7 1.9 2.3 5 (3) 15 (3) 31 (3) a backup sram on, rtc and lse off 2.4 2.6 3.0 6 (3) 20 (3) 40 (3) backup sram off, rtc on and lse in low drive mode 2.1 2.4 2.9 6 19 39 backup sram off, rtc on and lse in medium low drive mode 2.1 2.4 2.9 6 19 39 backup sram off, rtc on and lse in medium high drive mode 2.2 2.5 3.0 7 20 40 backup sram off, rtc on and lse in high drive mode 2.3 2.6 3.1 7 20 42 backup sram on, rtc on and lse in low drive mode 2.7 3.0 3.6 8 23 49 backup sram on, rtc on and lse in medium low drive mode 2.7 3.0 3.6 8 23 49 backup sram on, rtc on and lse in medium high drive mode 2.8 3.1 3.7 8 24 50 backup sram on, rtc on and lse in high drive mode 2.9 3.2 3.8 8 25 51 1. pdr is off for v dd =1.7v. when the pdr is off (internal reset off) , the typical current consumption is reduced by additional 1.2 a. 2. guaranteed by characterization results. 3. based on characterization, tested in production.
docid027589 rev 4 113/228 stm32f756xx electrical characteristics 196 table 33. typical and maximum current consumptions in v bat mode symbol parameter conditions (1) typ max (2) unit t a =25 c t a =85 c t a =105 c v bat = 1.7 v v bat = 2.4 v v bat = 3.3 v v bat = 3.6 v i dd_vbat supply current in v bat mode backup sram off, rtc and lse off 0.03 0.03 0.04 0.2 0.4 a backup sram on, rtc and lse off 0.74 0.75 0.78 3.0 7.0 backup sram off, rtc on and lse in low drive mode 0.40 0.52 0.72 2.8 6.5 backup sram off, rtc on and lse in medium low drive mode 0.40 0.52 0.72 2.8 6.5 backup sram off, rtc on and lse in medium high drive mode 0.54 0.64 0.85 3.3 7.6 backup sram off, rtc on and lse in high drive mode 0.62 0.73 0.94 3.6 8.4 backup sram on, rtc on and lse in low drive mode 1.06 1.18 1.41 5.4 12.7 backup sram on, rtc on and lse in medium low drive mode 1.16 1.28 1.51 5.8 13.6 backup sram on, rtc on and lse in medium high drive mode 1.18 1.3 1.54 5.9 13.8 backup sram on, rtc on and lse in high drive mode 1.36 1.48 1.73 6.7 15.5 1. crystal used: abracon abs07-120-32.768 khz-t with a c l of 6 pf for typical values. 2. guaranteed by characterization results.
electrical characteristics stm32f756xx 114/228 docid027589 rev 4 figure 25. typical v bat current consumption (rtc on/bkp sram off and lse in low drive mode) figure 26. typical v bat current consumption (rtc on/bkp sram off and lse in medium low drive mode) x? x? ? ?x? ? ?x? e ?e?? du???? x?s xs x?s ?s ?xes ?xs ?s ?x?s ?xs 069 ,''b9%$7x$ 069 ,''b9%$7x$ x? x? ? ?x? ? ?x? e ex? ?e?? du???? x?s xs x?s ?s ?xes ?xs ?s ?x?s ?xs
docid027589 rev 4 115/228 stm32f756xx electrical characteristics 196 figure 27. typical v bat current consumption (rtc on/bkp sram off and lse in medium high drive mode) figure 28. typical v bat current consumption (rtc on/bkp sram off and lse in high drive mode) x? x? ? ?x? ? ?x? e ex? ?e?? du???? x?s xs x?s ?s ?xes ?xs ?s ?x?s ?xs ,''b9%$7x$ 069 069 x? x? ? ?x? ? ?x? e ex? ?e?? du???? x? s xs x?s ?s ?xes ?xs ?s ?x?s ?xs ,''b9%$7x$
electrical characteristics stm32f756xx 116/228 docid027589 rev 4 figure 29. typical v bat current consumption (rtc on/bkp sram off and lse in high medium drive mode) i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 56: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 35: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o ? ? e ? ? ? ?e?? du????~ x?s xs x?s ?s ?xes ?xs ?s ?x?s ?xs ,''b9%$7x$ 069
docid027589 rev 4 117/228 stm32f756xx electrical characteristics 196 pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = table 34. switching output i/o current consumption (1) symbol parameter conditions i/o toggling frequency (fsw) mhz typ v dd = 3.3 v typ v dd = 1.8 v unit i ddio i/o switching current c ext = 0 pf c = c int + c s + c ext 2 0.1 0.1 ma 8 0.4 0.2 25 1.1 0.7 50 2.4 1.3 60 3.1 1.6 84 4.3 2.4 90 4.9 2.6 100 5.4 2.8 108 5.6 - c ext = 10 pf c = c int + c s + c ext 20.20.1 80.60.3 25 1.8 1.1 50 3.1 2.3 60 4.6 3.4 84 9.7 3.6 90 10.12 5.2 100 14.92 5.4 108 18.11 -
electrical characteristics stm32f756xx 118/228 docid027589 rev 4 on-chip peripheral current consumption the mcu is placed under the following conditions: ? at startup, all i/o pins are in analog input configuration. ? all peripherals are disabled unless otherwise mentioned. ? i/o compensation cell enabled. ? the art/l1-cache is on. ? scale 1 mode selected, internal digital voltage v12 = 1.32 v. ? hclk is the system clock. f pclk1 = f hclk /4, and f pclk2 = f hclk /2. the given value is calculated by measur ing the difference of current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ?f hclk = 216 mhz (scale 1 + over-drive on), f hclk = 168 mhz (scale 2), f hclk = 144 mhz (scale 3) ? ambient operating temperature is 25 c and v dd =3.3 v. i ddio i/o switching current c ext = 22 pf c = c int + c s + c ext 20.30.1 ma 81.00.5 25 3.5 1.6 50 5.9 4.2 60 10.0 4.4 84 19.12 5.8 90 19.6 - c ext = 33 pf c = c int + c s + c ext 20.30.2 81.30.7 25 3.5 2.3 50 10.26 5.19 60 16.53 - 1. cint + c s, pcb board capacitance including the pad pin is estimated to15 pf. table 34. switching output i/o current consumption (1) (continued) symbol parameter conditions i/o toggling frequency (fsw) mhz typ v dd = 3.3 v typ v dd = 1.8 v unit
docid027589 rev 4 119/228 stm32f756xx electrical characteristics 196 table 35. peripheral current consumption peripheral i dd (typ) (1) unit scale 1 scale 2 scale 3 ahb1 (up to 216 mhz) gpioa 2.2 2.1 1.9 a/mhz gpiob 2.1 1.8 1.7 gpioc 2.3 2.0 1.9 gpiod 2.2 1.9 1.8 gpioe 2.2 1.9 1.8 gpiof 2.2 1.9 1.8 gpiog 2.1 1.8 1.7 gpioh 2.0 1.7 1.7 gpioi 2.3 2.0 1.7 gpioj 2.2 1.9 1.7 gpiok 2.0 1.7 1.7 crc 1.0 0.9 0.8 bkpsram 0.8 0.7 0.6 dma1 2.7 x n + 5.1 2.6 x n + 4.7 2.2 x n + 4 dma2 2.2 x n + 4.9 2.6 x n + 4.4 2.2 x n + 4.1 dma2d 87.1 82.5 69.6 eth_mac eth_mac_tx eth_mac_rx eth_mac_ptp 42.1 39.7 34.1 otg_hs 57.5 54.4 47.6 otg_hs+ulpi ahb2 (up to 216 mhz) dcmi 5.1 4.7 4.0 a/mhz cryp 3.0 2.6 2.4 hash 4.2 3.7 3.3 rng 2.8 2.4 2.3 usb_otg_fs 31.8 29.9 25.8 ahb3 (up to 216 mhz) fmc 18.9 17.7 15.2 a/mhz qspi 23.2 21.8 18.5 bus matrix (2) 21.06 20.3 17.2 a/mhz
electrical characteristics stm32f756xx 120/228 docid027589 rev 4 apb1 (up to 54 mhz) tim2 19.8 18.7 16.1 a/mhz tim3 16.6 15.1 13.6 tim4 16.2 15.1 13.3 tim5 19 17.8 15.8 tim6 3 2.7 2.5 tim7 3 2.7 2.5 tim12 12.4 11.3 10.3 tim13 6 5.3 5 tim14 6 5.3 5 lptim1 9.4 8.7 8.1 wwdg 1.8 1.6 1.4 spi2/i2s2 (3) 32.92.8 spi3/i2s3 (3) 3.2 2.9 2.8 spdifrx 2.2 2 1.7 usart2 12.8 12 10.8 usart3 15.6 14.2 13.1 uart4 11.8 10.7 9.7 uart5 11.2 10 9.2 i2c1 9.8 8.7 7.8 i2c2 8.6 7.8 7.2 i2c3 8.6 7.8 7.2 i2c4 12 10.9 9.7 can1 6.8 6 5.6 can2 6.8 6 5.8 cec 1 0.7 0.8 pwr 1.2 0.9 0.8 dac (4) 32.72.5 uart7 12.4 11.6 10 uart8 10.4 9.3 8.6 table 35. peripheral current consumption (continued) peripheral i dd (typ) (1) unit scale 1 scale 2 scale 3
docid027589 rev 4 121/228 stm32f756xx electrical characteristics 196 apb2 (up to 108 mhz) tim1 25.2 23.9 20.4 a/mhz tim8 25.3 24 20.4 usart1 10.3 9.8 8.2 usart6 10.1 9.7 8.1 adc1 (5) 4.5 4.4 3.5 adc2 (5) 4.5 4.4 3.5 adc3 (5) 4.5 4.4 3.3 sdmmc1 8.5 7.9 6.7 spi1/i2s1 (3) 3.1 3 2.5 spi4 3.1 3 2.5 syscfg 1.5 1.4 1 tim9 8.8 8.4 6.9 tim10 5.6 5.2 4.3 tim11 5.4 5.2 4.3 spi5 3 2.8 2.2 spi6 3 2.8 2.2 sai1 3.4 3.3 2.6 sai2 3.3 3.2 2.5 ltdc 56.7 53.8 45.7 1. when the i/o compensation cell is on, i dd typical value increases by 0.22 ma. 2. the busmatrix is automatically active when at least one master is on. 3. to enable an i2s peripheral, first set the i2smod bit and then the i2se bit in the spi_i2scfgr register. 4. when the dac is on and en1/2 bits are set in da c_cr register, add an additional power consumption of 0.75 ma per dac channel for the analog part. 5. when the adc is on (adon bit set in the adc_cr 2 register), add an additional power consumption of 1.73 ma per adc for the analog part. table 35. peripheral current consumption (continued) peripheral i dd (typ) (1) unit scale 1 scale 2 scale 3
electrical characteristics stm32f756xx 122/228 docid027589 rev 4 5.3.8 wakeup time from low-power modes the wakeup times given in table 36 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep modes: the wakeup event is wfe. ? wkup (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd =3.3 v. table 36. low-power mode wakeup timings symbol parameter conditions typ (1) max (1) unit t wusleep (2) wakeup from sleep - 13 13 cpu clock cycles t wustop (2) wakeup from stop mode with mr/lp regulator in normal mode main regulator is on 14 14.9 s main regulator is on and flash memory in deep power down mode 104.1 107.6 low power regulator is on 21.4 24.2 low power regulator is on and flash memory in deep power down mode 111.5 116.5 t wustop (2) wakeup from stop mode with mr/lp regulator in under-drive mode main regulator in under-drive mode (flash memory in deep power-down mode) 107.4 113.2 low power regulator in under-drive mode (flash memory in deep power-down mode ) 112.7 120 twustdby (2) wakeup from standby mode exit standby mode on rising edge 308 313 exit standby mode on falling edge 307 313 1. guaranteed by characterization results. 2. the wakeup times are measured from the wakeup event to the point in which the appl ication code reads the first
docid027589 rev 4 123/228 stm32f756xx electrical characteristics 196 5.3.9 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard i/o. the external clock signal has to respect the table 56: i/o static characteristics . however, the recommended clock input waveform is shown in figure 30 . the characteristics given in table 37 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 17 . low-speed external user clock generated from an external source in bypass mode the lse oscillato r is switched off and the inpu t pin is a standard i/o. the external clock signal has to respect the table 56: i/o static characteristics . however, the recommended clock input waveform is shown in figure 31 . the characteristics given in table 38 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in table 17 . table 37. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) - 1-50mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design. 5-- ns t r(hse) t f(hse) osc_in rise or fall time (1) --10 c in(hse) osc_in input capacitance (1) --5-pf ducy (hse) duty cycle - 45 - 55 % i l osc_in input leakage current v ss v in v dd --1a
electrical characteristics stm32f756xx 124/228 docid027589 rev 4 figure 30. high-speed external clock source ac timing diagram table 38. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lse) t f(lse) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 c in(lse) osc32_in input capacitance (1) --5-pf ducy (lse) duty cycle - 30 - 70 % i l osc32_in input leakage current v ss v in v dd --1a 1. guaranteed by design. ai /3 # ?) . %xternal 34-& clocksource 6 (3%( t f(3% t 7(3% ) , 4 (3% t t r(3% t 7(3% f (3%?ext 6 (3%,
docid027589 rev 4 125/228 stm32f756xx electrical characteristics 196 figure 31. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 39 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 39. hse 4-26 mhz os cillator characteristics (1) 1. guaranteed by design. symbol parameter conditions min typ max unit f osc_in oscillator frequency - 4 - 26 mhz r f feedback resistor - - 200 - k i dd hse current consumption v dd =3.3 v, esr= 30 ? , c l =5 pf@25 mhz - 450 - a v dd =3.3 v, esr= 30 ? , c l =10 pf@25 mhz - 530 - acc hse (2) 2. this parameter depends on the crystal used in the application. the minimum and maximum values must be respected to comply with usb standard specifications. hse accuracy - ? 500 - 500 ppm g m _crit_max maximum critical crystal g m startup - - 1 ma/v t su(hse (3) 3. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is based on characterization results. it is measured for a standard crystal resonator and it can vary significant ly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms dl 2 6&b,1 ([whuqdo 670) forfnvrxufh 9 /6(+ w i/6( w :/6( , / 7 /6( w w u/6( w :/6( i /6(bh[w 9 /6(/
electrical characteristics stm32f756xx 126/228 docid027589 rev 4 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-freque ncy applications, and selected to match the requirements of the crystal or resonator (see figure 32 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 32. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all th e information given in this paragraph are based on characterization results obtained with typical external components specified in table 40 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion an d startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequenc y, package, accuracy). table 40. lse oscillator characteristics (f lse = 32.768 khz) (1) symbol parameter conditions min typ max unit i dd lse current consumption lsedrv[1:0]=00 low drive capability -250- na lsedrv[1:0]=10 medium low drive capability -300- lsedrv[1:0]=01 medium high drive capability -370- lsedrv[1:0]=11 high drive capability -480- dl 26&b28 7 26&b,1 i +6( & / 5 ) 670) 0+] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq 5 (;7 & /
docid027589 rev 4 127/228 stm32f756xx electrical characteristics 196 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 33. typical applicati on with a 32.768 khz crystal g m _crit_max maximum critical crystal g m lsedrv[1:0]=00 low drive capability - - 0.48 a/v lsedrv[1:0]=10 medium low drive capability - - 0.75 lsedrv[1:0]=01 medium high drive capability --1.7 lsedrv[1:0]=11 high drive capability --2.7 t su (2) start-up time v dd is stabilized - 2 - s 1. guaranteed by design. 2. guaranteed by characterization results. t su is the start-up time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal resonator and it can vary signif icantly with the crystal manufacturer. table 40. lse oscillator characteristics (f lse = 32.768 khz) (1) (continued) symbol parameter conditions min typ max unit dld 26&b 28 7 26&b ,1 i /6( & / 5 ) 670) n+] uhvrqdwru 5hvrqdwruzlwk lqwhjudwhgfdsdflwruv %ldv frqwuroohg jdlq & /
electrical characteristics stm32f756xx 128/228 docid027589 rev 4 5.3.10 internal clock source characteristics the parameters given in table 41 and table 42 are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 17 . high-speed internal (hsi) rc oscillator figure 34. hsi deviation versus temperature 1. guaranteed by characterization results. table 41. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 16 - mhz acc hsi hsi user trimming step (2) 2. guaranteed by design. ---1% accuracy of the hsi oscillator t a = ?40 to 105 c (3) 3. guaranteed by characterization results. ? 8-4.5% t a = ?10 to 85 c (3) ? 4- 4 % t a = 25 c (4) 4. factory calibrated, parts not soldered. ? 1- 1 % t su(hsi) (2) hsi oscillator startup time - - 2.2 4 s i dd(hsi) (2) hsi oscillator power consumption - - 60 80 a rx?9 rx9 rx?9 x9 x?9 x9 x?9 re ?? ?? ? ?? d~ d]v d? d??] o 069 7hpshudwxuh?& 1rupdol]hgghyldwlrq
docid027589 rev 4 129/228 stm32f756xx electrical characteristics 196 low-speed internal (lsi) rc oscillator figure 35. lsi deviation versus temperature 5.3.11 pll characteristics the parameters given in table 43 and table 44 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 17 . table 42. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. guaranteed by characterization results. frequency 17 32 47 khz t su(lsi) (3) 3. guaranteed by design. lsi oscillator startup time - 15 40 s i dd(lsi) (3) lsi oscillator power consumption - 0.4 0.6 a 069 7hpshudwxuh?& r?x9 rx9 rex9 r?x9 x9 ?x9 ex9 x9 ?x9 re ?? ?? ? ?? d]v d? d??] o 1rupdol]hgghyldwlrq table 43. main pll characteristics symbol parameter conditions min typ max unit f pll_in pll input clock (1) -0.95 (2) 12.10 mhz f pll_out pll multiplier output clock - 24 - 216 f pll48_out 48 mhz pll multiplier output clock - - 48 75 f vco_out pll vco output - 100 - 432
electrical characteristics stm32f756xx 130/228 docid027589 rev 4 t lock pll lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300 jitter (3) cycle-to-cycle jitter system clock 216 mhz rms - 25 - ps peak to peak - 150 - period jitter rms - 15 - peak to peak - 200 - main clock output (mco) for rmii ethernet cycle to cycle at 50 mhz on 1000 samples -32 - main clock output (mco) for mii ethernet cycle to cycle at 25 mhz on 1000 samples -40 - bit time can jitter cycle to cycle at 1 mhz on 1000 samples -330 - i dd(pll) (4) pll power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pll) (4) pll power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between pll and plli2s. 2. guaranteed by design. 3. the use of 2 plls in parallel could degraded the jitter up to +30%. 4. guaranteed by characterization results. table 43. main pll characteristics (continued) symbol parameter conditions min typ max unit table 44. plli2s characteristics symbol parameter conditions min typ max unit f plli2s_in plli2s input clock (1) -0.95 (2) 12.10 mhz f plli2sp_out plli2s multiplier output clock for spdifrx - - - 216 f plli2sq_out plli2s multiplier output clock for sai - - - 216 f plli2sr_out plli2s multiplier output clock for i2s - - - 216 f vco_out plli2s vco output - 100 - 432 t lock plli2s lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
docid027589 rev 4 131/228 stm32f756xx electrical characteristics 196 jitter (3) master i2s clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps ws i2s clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(plli2s) (4) plli2s power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(plli2s) (4) plli2s power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed by characterization results. table 44. plli2s characteristics (continued) symbol parameter conditions min typ max unit table 45. pllisai characteristics symbol parameter conditions min typ max unit f pllsai_in pllsai input clock (1) -0.95 (2) 12.10 mhz f pllsaip_out pllsai multiplier output clock for 48 mhz - - 48 75 f pllsaiq_out pllsai multiplier output clock for sai - - - 216 f pllsair_out pllsai multiplier output clock for lcd-tft - - - 216 f vco_out pllsai vco output - 100 - 432 t lock pllsai lock time vco freq = 100 mhz 75 - 200 s vco freq = 432 mhz 100 - 300
electrical characteristics stm32f756xx 132/228 docid027589 rev 4 5.3.12 pll spread spec trum clock generation (sscg) characteristics the spread spectrum clock generation (sscg) feature allows to reduce electromagnetic interferences (see table 52: emi characteristics ). it is available only on the main pll. equation 1 the frequency modulation period (modeper) is given by the equation below: f pll_in and f mod must be expressed in hz. as an example: if f pll_in = 1 mhz, and f mod = 1 khz, the modulation depth (modeper) is given by equation 1: jitter (3) master sai clock jitter cycle to cycle at 12.288 mhz on 48khz period, n=432, r=5 rms - 90 - peak to peak - 280 - ps average frequency of 12.288 mhz n = 432, r = 5 on 1000 samples -90 -ps fs clock jitter cycle to cycle at 48 khz on 1000 samples -400 - ps i dd(pllsai) (4) pllsai power consumption on v dd vco freq = 100 mhz vco freq = 432 mhz 0.15 0.45 - 0.40 0.75 ma i dda(pllsai) (4) pllsai power consumption on v dda vco freq = 100 mhz vco freq = 432 mhz 0.30 0.55 - 0.40 0.85 ma 1. take care of using the appropriate division fact or m to have the specifie d pll input clock values. 2. guaranteed by design. 3. value given with main pll running. 4. guaranteed by characterization results. table 45. pllisai characteristics (continued) symbol parameter conditions min typ max unit table 46. sscg parameters constraint symbol parameter min typ max (1) unit f mod modulation frequency - - 10 khz md peak modulation depth 0.25 - 2 % modeper * incstep - - - 2 15 ? 1- 1. guaranteed by design. modeper round f pll_in 4f mod () ? [] = modeper round 10 6 410 3 () ? [] 250 ==
docid027589 rev 4 133/228 stm32f756xx electrical characteristics 196 equation 2 equation 2 allows to calculate the increment step (incstep): f vco_out must be expressed in mhz. with a modulation depth (md) = 2 % (4 % peak to peak), and plln = 240 (in mhz): an amplitude quantization error may be generat ed because the linear modulation profile is obtained by taking the quantized values (roun ded to the nearest integer) of modper and incstep. as a result, the achieved modulation depth is quantized. the percentage quantized modulation depth is given by the following formula: as a result: figure 36 and figure 37 show the main pll output clock waveforms in center spread and down spread modes, where: f0 is f pll_out nominal. t mode is the modulation period. md is the modulation depth. figure 36. pll output clock waveforms in center spread mode incstep round 2 15 1 ? () md plln () 100 5 modeper () ? [] = incstep round 2 15 1 ? () 2240 () 100 5 250 () ? [] 126md(quantitazed)% == md quantized % modeper incstep 100 5 () 2 15 1 ? () plln () ? = md quantized % 250 126 100 5 () 2 15 1 ? () 240 () ? 2.002%(peak) == &requency0,,?/54 4ime & tmode xtmode md ai md
electrical characteristics stm32f756xx 134/228 docid027589 rev 4 figure 37. pll output clock waveforms in down spread mode 5.3.13 memory characteristics flash memory the characteristics are given at ta = ? 40 to 105 c unless otherwise specified. the devices are shipped to customers with the flash memory erased. )uhtxhqf\3//b287 7lph ) wprgh [wprgh [pg dle table 47. flash memory characteristics symbol parameter conditions min typ max unit i dd supply current write / erase 8-bit mode, v dd = 1.7 v - 14 - ma write / erase 16-bit mode, v dd = 2.1 v - 17 - write / erase 32-bit mode, v dd = 3.3 v - 24 - table 48. flash memory programming symbol parameter conditions min (1) typ max (1) unit t prog word programming time program/erase parallelism (psize) = x 8/16/32 -16100 (2) s t erase32kb sector (32 kb) erase time program/erase parallelism (psize) = x 8 - 400 800 ms program/erase parallelism (psize) = x 16 - 250 600 program/erase parallelism (psize) = x 32 - 200 500 t erase128kb sector (128 kb) erase time program/erase parallelism (psize) = x 8 - 1100 2400 ms program/erase parallelism (psize) = x 16 - 800 1400 program/erase parallelism (psize) = x 32 - 500 1100
docid027589 rev 4 135/228 stm32f756xx electrical characteristics 196 t erase256kb sector (256 kb) erase time program/erase parallelism (psize) = x 8 -2.14 s program/erase parallelism (psize) = x 16 -1.52.6 program/erase parallelism (psize) = x 32 -12 t me mass erase time program/erase parallelism (psize) = x 8 -816 s program/erase parallelism (psize) = x 16 -5.611.2 program/erase parallelism (psize) = x 32 -48 v prog programming voltage 32-bit program operation 2.7 - 3 v 16-bit program operation 2.1 - 3.6 v 8-bit program operation 1.7 - 3.6 v 1. guaranteed by characterization results. 2. the maximum programming time is m easured after 100k erase operations. table 49. flash memory programming with v pp symbol parameter conditions min (1) typ max (1) 1. guaranteed by design. unit t prog double word programming t a = 0 to +40 c v dd = 3.3 v v pp = 8.5 v -16100 (2) 2. the maximum programming time is measured after 100k erase operations. s t erase32kb sector (32 kb) erase time - 180 - ms t erase128kb sector (128 kb) erase time - 450 - t erase256kb sector (256 kb) erase time - 900 - t me mass erase time - 6.9 - s v prog programming voltage - 2.7 - 3.6 v v pp v pp voltage range - 7 - 9 v i pp minimum current sunk on the v pp pin -10--ma t vpp (3) 3. v pp should only be connected during programming/erasing. cumulative time during which v pp is applied - - - 1 hour table 48. flash memory programming (continued) symbol parameter conditions min (1) typ max (1) unit
electrical characteristics stm32f756xx 136/228 docid027589 rev 4 5.3.14 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 51 . they are based on the ems levels and classes defined in application note an1709. as a consequence, it is recommended to add a serial resistor (1 k ? ) located as close as possible to the mcu to the pins exposed to noise (connected to tracks longer than 50 mm on pcb). table 50. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. guaranteed by characterization results. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 table 51. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp176, t a = +25 c, f hclk = 216 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, tfbga216, t a =+25 c, f hclk = 216 mhz, conforms to iec 61000-4-2 4a
docid027589 rev 4 137/228 stm32f756xx electrical characteristics 196 designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application, executing eembc code, is running. this emission test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. table 52. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f cpu ] unit 25/200 mhz s emi peak level v dd = 3.6 v, t a = 25 c, tfbga216 package, conforming to iec61967-2 art/l1-cache off, over-drive on, all periphe ral clocks enabled, clock dithering disabled. 0.1 to 30 mhz - 4 dbv 30 to 130 mhz 9 130 mhz to 1ghz 11 emi level 3 - v dd = 3.6 v, t a = 25 c, tfbga216 package, conforming to iec61967-2 art/l1-cache on, over-drive on, all periphe ral clocks enabled, clock dithering disabled. 0.1 to 30 mhz 4 dbv 30 to 130 mhz 5 130 mhz to 1ghz 14 emi level 3 - v dd = 3.6 v, t a = 25 c, tfbga216 package, conforming to iec61967-2 art/l1-cache on, over-drive on, all periphe ral clocks enabled, clock dithering enabled. 0.1 to 30 mhz - 9 dbv 30 to 130 mhz -7 130 mhz to 1ghz -5 emi level 1.5 -
electrical characteristics stm32f756xx 138/228 docid027589 rev 4 5.3.15 absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ans i/esda/jedec js-001-2012 and an si/esd s5.3.1-2 009 standards. static latchup two complementary static te sts are required on six pa rts to assess the latchup performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latchup standard. 5.3.16 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibilty to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. table 53. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c conforming to ansi/esda/jedec js-001-2012 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c conforming to ansi/esd s5.3.1-2009, lqfp100, lqfp144, lqfp176, lqfp208, wlcsp143, ufbga176, tfbga100 and tfbga216 packages c3 250 1. guaranteed by characterization results. table 54. electric al sensitivities symbol parameter c onditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a
docid027589 rev 4 139/228 stm32f756xx electrical characteristics 196 the failure is indicated by an out of range parameter: adc error above a certain limit (>5 lsb tue), out of conventional limits of induc ed leakage current on adjacent pins (out of ? 5 a/+0 a range), or other functi onal failure (for example reset, oscillator frequency deviation). negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. the test results are given in table 55 . note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 5.3.17 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 56: i/o static characteristics are derived from tests performed under the conditions summarized in table 17 . all i/os are cmos and ttl compliant. table 55. i/o current injection susceptibility (1) symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot pin ? 0na ma injected current on nrst pin ? 0na injected current on pa0, pc0 pins ? 0na injected current on any other ft pin ? 5na injected current on any other pins ? 5+5 1. na = not applicable . table 56. i/o static characteristics symbol parameter conditions min typ max unit v il ft, tta and nrst i/o input low level voltage 1.7 v v dd 3.6 v - - 0.35v dd ? 0.04 (1) v 0.3v dd (2) boot i/o input low level voltage 1.75 v v dd 3.6 v, ? 40 c t a 105 c -- 0.1v dd +0.1 (1) 1.7 v v dd 3.6 v, 0 c t a 105 c --
electrical characteristics stm32f756xx 140/228 docid027589 rev 4 v ih ft, tta and nrst i/o input high level voltage (5) 1.7 v v dd 3.6 v 0.45v dd +0.3 (1) -- v 0.7v dd (2) boot i/o input high level voltage 1.75 v v dd 3.6 v, ? 40 c t a 105 c 0.17v dd +0.7 (1) -- 1.7 v v dd 3.6 v, 0 c t a 105 c v hys ft, tta and nrst i/o input hysteresis 1.7 v v dd 3.6 v 10%v dd (3) -- v boot i/o input hysteresis 1.75 v v dd 3.6 v, ? 40 c t a 105 c 0.1 - - 1.7 v v dd 3.6 v, 0 c t a 105 c i lkg i/o input leakage current (4) v ss v in v dd -- 1 a i/o ft input leakage current (5) v in = 5 v - - 3 r pu weak pull-up equivalent resistor (6) all pins except for pa10/pb12 (otg_fs_id ,otg_hs_id ) v in = v ss 30 40 50 k pa10/pb12 (otg_fs_id ,otg_hs_id ) 71014 r pd weak pull- down equivalent resistor (7) all pins except for pa10/pb12 (otg_fs_id ,otg_hs_id ) v in = v dd 30 40 50 pa10/pb12 (otg_fs_id ,otg_hs_id ) 71014 c io (8) i/o pin capacitance - - 5 - pf 1. guaranteed by design. 2. tested in production. 3. with a minimum of 200 mv. 4. leakage could be higher than the maximum value, if nega tive current is injected on adjacent pins, refer to table 55: i/o current injection susceptibility 5. to sustain a voltage higher than vdd +0.3 v, the internal pull-up/pull-down resistors mu st be disabled. leakage could be higher than the maximum value, if negative current is injected on adjacent pins.refer to table 55: i/o current injection susceptibility 6. pull-up resistors are designed with a true resistance in seri es with a switchable pmos. th is pmos contribution to the series resistance is minimum (~10% order). table 56. i/o static characteristics (continued) symbol parameter conditions min typ max unit
docid027589 rev 4 141/228 stm32f756xx electrical characteristics 196 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements for ft i/os is shown in figure 38 . figure 38. ft i/o input characteristics output driving current the gpios (general purpose input/outputs) can sink or source up to 8 ma, and sink or source up to 20 ma (with a relaxed v ol /v oh ) except pc13, pc14, pc15 and pi8 which can sink or source up to 3ma. when using the pc13 to pc15 and pi8 gpios in output mode, the speed should not exceed 2 mhz with a maximum load of 30 pf. in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 5.2 . in particular: ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 15 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 15 ). 7. pull-down resistors are designed with a tr ue resistance in series with a switchabl e nmos. this nmos contribution to the series resistance is minimum (~10% order). 8. hysteresis voltage between schmitt trigger switch ing levels. guaranteed by characterization results. 069 9''9 9,/9,+9 7hvwhglqsurgxfwlrq&026uhtxluhphqw9,+plq 9'' 7hvwhglqsurgxfwlrq&026uhtxluhphqw9,/pd[ 9'' %dvhgrq'hvljqvlpxodwlrqv9,/pd[ 9'' 77/uhtxluhphqw 9,+plq 9 77/uhtxluhphqw9,/pd[ 9 $uhdqrw ghwhuplqhg %dvhgrq'hvljqvlpxodwlrqv9,+plq 9''
electrical characteristics stm32f756xx 142/228 docid027589 rev 4 output voltage levels unless otherwise specified, the parameters given in table 57 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . all i/os are cmos and ttl compliant. table 57. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximum rating specified in table 15 . and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v v dd 3.6 v 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. -0.4 v v oh (3) 3. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin except pc14 cmos port (2) i io = -8 ma 2.7 v v dd 3.6 v v dd ? 0.4 - v oh (3) output high level voltage for pc14 cmos port (2) i io = -2 ma 2.7 v v dd 3.6 v v dd ? 0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io =+8ma 2.7 v v dd 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin except pc14 ttl port (2) i io =-8ma 2.7 v v dd 3.6 v 2.4 - v ol (1) output low level voltage for an i/o pin i io = +20 ma 2.7 v v dd 3.6 v -1.3 (4) 4. based on characterization data. v v oh (3) output high level voltage for an i/o pin except pc14 i io = -20 ma 2.7 v v dd 3.6 v v dd ? 1.3 (4) - v ol (1) output low level voltage for an i/o pin i io = +6 ma 1.8 v v dd 3.6 v -0.4 (4) v v oh (3) output high level voltage for an i/o pin except pc14 i io = -6 ma 1.8 v v dd 3.6 v v dd ? 0.4 (4) - v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.7 v v dd 3.6v -0.4 (5) 5. guaranteed by design. v v oh (3) output high level voltage for an i/o pin except pc14 i io = -4 ma 1.7 v v dd 3.6v v dd ? 0.4 (5) - v oh (3) output high level voltage for pc14 i io = -1 ma 1.7 v v dd 3.6v v dd ? 0.4 (5) -
docid027589 rev 4 143/228 stm32f756xx electrical characteristics 196 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 39 and table 58 , respectively. unless otherwise specified, the parameters given in table 58 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 17 . table 58. i/o ac characteristics (1)(2) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit 00 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 4 mhz c l = 50 pf, v dd 1.7 v - - 2 c l = 10 pf, v dd 2.7 v - - 8 c l = 10 pf, v dd 1.8 v - - 4 c l = 10 pf, v dd 1.7 v - - 3 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd = 1.7 v to 3.6 v --100ns 01 f max(io)out maximum frequency (3) c l = 50 pf, v dd 2.7 v - - 25 mhz c l = 50 pf, v dd 1.8 v - - 12.5 c l = 50 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 2.7 v - - 50 c l = 10 pf, v dd 1.8 v - - 20 c l = 10 pf, v dd 1.7 v - - 12.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 50 pf, v dd 2.7 v - - 10 ns c l = 10 pf, v dd 2.7 v - - 6 c l = 50 pf, v dd 1.7 v - - 20 c l = 10 pf, v dd 1.7 v - - 10 10 f max(io)out maximum frequency (3) c l = 40 pf, v dd 2.7 v - - 50 (4) mhz c l = 10 pf, v dd 2.7 v - - 100 (4) c l = 40 pf, v dd 1.7 v - - 25 c l = 10 pf, v dd 1.8 v - - 50 c l = 10 pf, v dd 1.7 v - - 42.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 40 pf, v dd 2.7 v - - 6 ns c l = 10 pf, v dd 2.7 v - - 4 c l = 40 pf, v dd 1.7 v - - 10 c l = 10 pf, v dd 1.7 v - - 6
electrical characteristics stm32f756xx 144/228 docid027589 rev 4 figure 39. i/o ac charac teristics definition 11 f max(io)out maximum frequency (3) c l = 30 pf, v dd 2.7 v - - 100 (4) mhz c l = 30 pf, v dd 1.8 v - - 50 c l = 30 pf, v dd 1.7 v - - 42.5 c l = 10 pf, v dd 2.7 v - - 180 (4) c l = 10 pf, v dd 1.8 v - - 100 c l = 10 pf, v dd 1.7 v - - 72.5 t f(io)out / t r(io)out output high to low level fall time and output low to high level rise time c l = 30 pf, v dd 2.7 v - - 4 ns c l = 30 pf, v dd 1.8 v - - 6 c l = 30 pf, v dd 1.7 v - - 7 c l = 10 pf, v dd 2.7 v - - 2.5 c l = 10 pf, v dd 1.8 v - - 3.5 c l = 10 pf, v dd 1.7 v - - 4 - textipw pulse width of external signals detected by the exti controller -10--ns 1. guaranteed by design. 2. the i/o speed is configured using t he ospeedry[1:0] bits. refer to the stm32f75xxx and stm32f74xxx reference manual for a description of the gpiox_ speedr gpio port output speed register. 3. the maximum frequency is defined in figure 39 . 4. for maximum frequencies above 50 mhz and v dd > 2.4 v, the compensation cell should be used. table 58. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] bit value (1) symbol parameter conditions min typ max unit dlg w u,2rxw 287387 (;7(51$/ 21&/ 0d[lpxpiuhtxhqf\lvdfklhyhgliw u w i ?7dqgliwkhgxw\f\fohlv zkhqordghge\& / vshflilhglqwkhwdeoh3 ,2$&fkdudfwhulvwlfv 7 w i,2rxw
docid027589 rev 4 145/228 stm32f756xx electrical characteristics 196 5.3.18 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 56: i/o static characteristics ). unless otherwise specified, the parameters given in table 59 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in table 17 . figure 40. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 59 . otherwise the reset is not taken into account by the device. table 59. nrst pin characteristics symbol parameter conditions min typ max unit r pu weak pull-up equivalent resistor (1) v in = v ss 30 40 50 k v f(nrst) (2) nrst input filtered pulse - - - 100 ns v nf(nrst) (2) nrst input not filtered pulse v dd > 2.7 v 300 - - ns t nrst_out generated reset pulse duration internal reset source 20 - - s 1. the pull-up is designed with a true resistance in seri es with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 2. guaranteed by design. dlf 670) 5 38 1567 9 '' )lowhu ,qwhuqdo5hvhw ?) ([whuqdo uhvhwflufxlw
electrical characteristics stm32f756xx 146/228 docid027589 rev 4 5.3.19 tim time r characteristics the parameters given in table 60 are guaranteed by design. refer to section 5.3.17: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 5.3.20 rtc characteristics 5.3.21 12-bit adc characteristics unless otherwise specified, the parameters given in table 62 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions su mmarized in table 17 . table 60. timx characteristics (1)(2) 1. timx is used as a general term to refer to the tim1 to tim12 timers. 2. guaranteed by design. symbol parameter conditions (3) 3. the maximum timer frequency on apb1 or apb2 is up to 216 mhz, by setting the timpre bit in the rcc_dckcfgr register, if apbx prescaler is 1 or 2 or 4, then timxclk = hclk, otherwise timxclk = 4x pclkx. min max unit t res(tim) timer resolution time ahb/apbx prescaler=1 or 2 or 4, f timxclk = 216 mhz 1- t timxclk ahb/apbx prescaler>4, f timxclk = 108 mhz 1- t timxclk f ext timer external clock frequency on ch1 to ch4 f timxclk = 216 mhz 0 f timxclk /2 mhz res tim timer resolution - 16/32 bit t max_count maximum possible count with 32-bit counter -- 65536 65536 t timxclk table 61. rtc characteristics symbol parameter conditions min max -f pclk1 /rtcclk frequency ratio any read/write operation from/to an rtc register 4- table 62. adc characteristics symbol parameter conditions min typ max unit v dda power supply v dda ? v ref+ < 1.2 v 1.7 (1) -3.6v v ref+ positive reference voltage 1.7 (1) -v dda v v ref- negative reference voltage - - 0 - v
docid027589 rev 4 147/228 stm32f756xx electrical characteristics 196 f adc adc clock frequency v dda = 1.7 (1) to 2.4 v 0.6 15 18 mhz v dda = 2.4 to 3.6 v 0.6 30 36 mhz f trig (2) external trigger frequency f adc = 30 mhz, 12-bit resolution - - 1764 khz ---171/f adc v ain conversion voltage range (3) - 0 (v ssa or v ref- tied to ground) -v ref+ v r ain (2) external input impedance see equation 1 for details --50k r adc (2)(4) sampling switch resistance - - - 6 k c adc (2) internal sample and hold capacitor --47pf t lat (2) injection trigger conversion latency f adc = 30 mhz - - 0.100 s --3 (5) 1/f adc t latr (2) regular trigger conversion latency f adc = 30 mhz - - 0.067 s --2 (5) 1/f adc t s (2) sampling time f adc = 30 mhz 0.100 - 16 s - 3 - 480 1/f adc t stab (2) power-up time - - 2 3 s t conv (2) total conversion time (including sampling time) f adc = 30 mhz 12-bit resolution 0.50 - 16.40 s f adc = 30 mhz 10-bit resolution 0.43 - 16.34 s f adc = 30 mhz 8-bit resolution 0.37 - 16.27 s f adc = 30 mhz 6-bit resolution 0.30 - 16.20 s 9 to 492 (t s for sampling +n-bit re solution for successive approximation) 1/f adc f s (2) sampling rate (f adc = 30 mhz, and t s = 3 adc cycles) 12-bit resolution single adc - - 2 msps 12-bit resolution interleave dual adc mode - - 3.75 msps 12-bit resolution interleave triple adc mode - - 6 msps table 62. adc characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics stm32f756xx 148/228 docid027589 rev 4 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. n = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the adc_smpr1 register. i vref+ (2) adc v ref dc current consumption in conversion mode - - 300 500 a i vdda (2) adc v dda dc current consumption in conversion mode --1.61.8ma 1. v dda minimum value of 1.7 v is obtained with the us e of an external power supply supervisor (refer to section 2.17.2: internal reset off ). 2. guaranteed by characterization results. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. r adc maximum value is given for v dd =1.7 v, and minimum value for v dd =3.3 v. 5. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 62 . table 62. adc characteristics (continued) symbol parameter conditions min typ max unit table 63. adc static accuracy at f adc = 18 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization results. unit et total unadjusted error f adc =18 mhz v dda = 1.7 to 3.6 v v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 3 4 lsb eo offset error 2 3 eg gain error 1 3 ed differential linearity error 1 2 el integral linearity error 2 3 table 64. adc static accuracy at f adc = 30 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization results. unit et total unadjusted error f adc = 30 mhz, r ain < 10 k , v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v, v dda ? v ref < 1.2 v 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 4 ed differential linearity error 1 2 el integral linearity error 1.5 3 r ain k0.5 ? () f adc c adc 2 n 2 + () ln ---------------------------------------------------------------- r adc ? =
docid027589 rev 4 149/228 stm32f756xx electrical characteristics 196 note: adc accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this signifi cantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 5.3.17 does not affect the adc accuracy. table 65. adc static accuracy at f adc = 36 mhz symbol parameter test conditions typ max (1) 1. guaranteed by characterization results. unit et total unadjusted error f adc =36 mhz, v dda = 2.4 to 3.6 v, v ref = 1.7 to 3.6 v v dda ? v ref < 1.2 v 4 7 lsb eo offset error 2 3 eg gain error 3 6 ed differential linearity error 2 3 el integral linearity error 3 6 table 66. adc dynamic accuracy at f adc = 18 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =18 mhz v dda = v ref+ = 1.7 v input frequency = 20 khz temperature = 25 c 10.3 10.4 - bits sinad signal-to-noise and distortion ratio 64 64.2 - db snr signal-to-noise ratio 64 65 - thd total harmonic distortion ? 67 ? 72 - 1. guaranteed by characterization results. table 67. adc dynamic accuracy at f adc = 36 mhz - limited test conditions (1) symbol parameter test conditions min typ max unit enob effective number of bits f adc =36 mhz v dda = v ref+ = 3.3 v input frequency = 20 khz temperature = 25 c 10.6 10.8 - bits sinad signal-to noise and distortion ratio 66 67 - db snr signal-to noise ratio 64 68 - thd total harmonic distortion ? 70 ? 72 - 1. guaranteed by characterization results.
electrical characteristics stm32f756xx 150/228 docid027589 rev 4 figure 41. adc accuracy characteristics 1. see also table 64 . 2. example of an actual transfer curve. 3. ideal transfer curve. 4. end point correlation line. 5. e t = total unadjusted error: maximum deviation be tween the actual and the ideal transfer curves. eo = offset error: deviation between the fi rst actual transition and the first ideal one. eg = gain error: deviation between the last ideal transition and the last actual one. ed = differential linearity error: maximum deviation between actual steps and the ideal one. el = integral linearity error: maximum deviati on between any actual transition and the end point correlation line. figure 42. typical connecti on diagram using the adc 1. refer to table 62 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 5 pf). a high c parasitic value downgrades conversion accuracy. to remedy this, f adc should be reduced. aic % / % ' , 3" )$%!, % 4 % $ % , 6 $$! 6 33! 6 2%& ordependingonpackage = 6 $$! ;,3" )$%!, dl 670) 9 '' $,1[ , / ??$ 9 9 7 5 $,1 & sdudvlwlf 9 $,1 9 9 7 5 $'& & $'& elw frqyhuwhu 6dpsohdqgkrog$'& frqyhuwhu
docid027589 rev 4 151/228 stm32f756xx electrical characteristics 196 general pcb design guidelines power supply decoupling should be performed as shown in figure 43 or figure 44 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 43. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ input is available on all the pa ckages except tfbga100 whereas the v ref? is available only on ufbga176 and tfbga216. when v ref- is not available, it is internally connected to v dda and v ssa . figure 44. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ input is available on all the pack ages except tfbga100, whereas the v ref? is available only on ufbga176 and tfbga216. when v ref- is not available, it is internally connected to v dda and v ssa . 670) ?)q) ?)q) 9 5() 9 ''$ 9 66$ 9 5() dle 670) ?)q) dlf 9 5() 9 ''$ 9 5() 9 66$
electrical characteristics stm32f756xx 152/228 docid027589 rev 4 5.3.22 temperature sensor characteristics 5.3.23 v bat monitoring characteristics 5.3.24 reference voltage the parameters given in table 71 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 17 . table 68. temperature sensor characteristics symbol parameter min typ max unit t l (1) v sense linearity with temperature - 1 2c avg_slope (1) average slope - 2.5 - mv/c v 25 (1) voltage at 25 c - 0.76 - v t start (2) startup time - 6 10 s t s_temp (2) adc sampling time when reading the temperature (1 c accuracy) 10 - - s 1. guaranteed by characterization results. 2. guaranteed by design. table 69. temperature sensor calibration values symbol parameter memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1ff0 f44c - 0x1ff0 f44d ts_cal2 ts adc raw data acquired at temperature of 110 c, v dda = 3.3 v 0x1ff0 f44e - 0x1ff0 f44f table 70. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement - 4 - - er (1) error on q ?1 - +1 % t s_vbat (2)(2) adc sampling time when reading the v bat 1 mv accuracy 5- -s 1. guaranteed by design. 2. shortest sampling time can be determined in the application by multiple iterations. table 71. internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.18 1.21 1.24 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -10--s v rerint_s (2) internal reference voltage spread over the temperature range v dd = 3v 10mv - 3 5 mv
docid027589 rev 4 153/228 stm32f756xx electrical characteristics 196 5.3.25 dac electri cal characteristics t coeff (2) temperature coefficient - - 30 50 ppm/c t start (2) startup time - - 6 10 s 1. shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design. table 71. internal reference voltage (continued) symbol parameter conditions min typ max unit table 72. internal reference voltage calibration values symbol parameter memory address v refin_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1ff0 f44a - 0x1ff0 f44b table 73. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 1.7 (1) -3.6 v - v ref+ reference supply voltage 1.7 (1) -3.6vv ref+ v dda v ssa ground 0- 0v - r load (2) resistive load with buffer on 5 - - k - r o (2) impedance output with buffer off --15k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (2) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (2) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x1c7) to (0xe38) at v ref+ = 1.7 v dac_out max (2) higher dac_out voltage with buffer on -- v dda ? 0.2 v dac_out min (2) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (2) higher dac_out voltage with buffer off -- v ref+ ? 1lsb v i vref+ (4) dac dc v ref current consumption in quiescent mode (standby mode) -170240 a with no load, worst code (0x800) at v ref+ = 3.6 v in terms of dc consumption on the inputs -5075 with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs
electrical characteristics stm32f756xx 154/228 docid027589 rev 4 i dda (4) dac dc v dda current consumption in quiescent mode (3) -280380a with no load, middle code (0x800) on the inputs -475625a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (4) differential non linearity difference between two consecutive code-1lsb) - - 0.5 lsb given for the dac in 10-bit configuration. - - 2 lsb given for the dac in 12-bit configuration. inl (4) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) - - 1 lsb given for the dac in 10-bit configuration. - - 4 lsb given for the dac in 12-bit configuration. offset (4) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) - - 10 mv given for the dac in 12-bit configuration --3lsb given for the dac in 10-bit at v ref+ = 3.6 v --12lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (4) gain error - - 0.5 % given for the dac in 12-bit configuration t settling (4) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 4lsb -3 6s c load 50 pf, r load 5 k thd (4) total harmonic distortion buffer on -- -db c load 50 pf, r load 5 k update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1ms/s c load 50 pf, r load 5 k t wakeup (4) wakeup time from off state (setting the enx bit in the dac control register) -6.510s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (2) power supply rejection ratio (to v dda ) (static dc measurement) - ?67 ?40 db no r load , c load = 50 pf 1. v dda minimum value of 1.7 v is obtained with the use of an external power suppl y supervisor (refer to section 2.17.2: internal reset off ). 2. guaranteed by design. 3. the quiescent mode corresponds to a state where the dac maintains a stable output level to ensure that no dynamic consumption occurs. 4. guaranteed by characterization results. table 73. dac characteristics (continued) symbol parameter min typ max unit comments
docid027589 rev 4 155/228 stm32f756xx electrical characteristics 196 figure 45. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. 5.3.26 communications interfaces i 2 c interface characteristics the i 2 c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s. ? fast-mode plus (fm+): with a bit rate up to 1mbit/s. the i 2 c timings requirements are guaranteed by de sign when the i2c peripheral is properly configured (refer to rm0385 reference manual) and when the i2cclk frequency is greater than the minimum shown in the table below: the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. 5 / & / %xiihuhg1rqexiihuhg'$& '$&b287[ %xiihu elw gljlwdowr dqdorj frqyhuwhu ai6 table 74. minimum i2cclk frequency in all i2c modes symbol parameter condition min unit f(i2cclk) i2cclk frequency standard-mode 2 mhz fast-mode analog filtre on dnf=0 10 analog filtre off dnf=1 9 fast-mode plus analog filtre on dnf=0 22.5 analog filtre off dnf=1 16
electrical characteristics stm32f756xx 156/228 docid027589 rev 4 the 20ma output drive requirement in fast-m ode plus is not supported. this limits the maximum load cload supported in fm+, which is given by these formulas: ? tr(sda/scl)=0.8473xr p xc load ? r p (min)= (vdd-v ol (max))/i ol (max) where rp is the i2c lin es pull-up. refer to section 5.3.17: i/o port characteristics for the i2c i/os characteristics. all i 2 c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 75. i2c analog filter characteristics (1) 1. guaranteed by characterization results. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 150 (3) 3. spikes with widths above t af(max) are not filtered ns
docid027589 rev 4 157/228 stm32f756xx electrical characteristics 196 spi interface characteristics unless otherwise specified, the parameters given in table 76 for the spi interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 5.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 76. spi dynamic characteristics (1) symbol parameter cond itions min typ max unit f sck 1/t c(sck) spi clock frequency master mode spi1,4,5,6 2.7 vdd 3.6 -- 54 (2) mhz master mode spi1,4,5,6 1.71 vdd 3.6 27 master transmitter mode spi1,4,5,6 1.71 vdd 3.6 54 slave receiver mode spi1,4,5,6 1.71 vdd 3.6 54 slave mode transmitter/full duplex spi1,4,5,6 2.7 vdd 3.6 50 (3) slave mode transmitter/full duplex spi1,4,5,6 1.71 vdd 3.6 38 (3) master & slave mode spi2,3 1.71 vdd 3.6 27 tsu(nss) nss setup time slave mode, spi presc = 2 4*tpclk - - ns th(nss) nss hold time slave mode, spi presc = 2 2*tpclk - - tw(sckh) tw(sckl) sck high and low time master mode tpclk-2 tpclk tpclk+2
electrical characteristics stm32f756xx 158/228 docid027589 rev 4 figure 46. spi timing diagram - slave mode and cpha = 0 tsu(mi) data input setup time master mode 5.5 - - ns tsu(si) slave mode 4 - - th(mi) data input hold time master mode 4 - - th(si) slave mode 2 - - ta(so) data output access time slave mode 7 - 21 tdis(so) data output disable time slave mode 5 - 12 tv(so) data output valid time slave mode 2.7 vdd 3.6v - 6.5 10 slave mode 1.71 vdd 3.6v - 6.5 13 tv(mo) master mode - 2 4 th(so) data output hold time slave mode 1.71 vdd 3.6v 5.5 - - th(mo) master mode 0 - - 1. guaranteed by characterization results. 2. excepting spi1 with sck io pin mapped on pa5. in this configuration, maximum ac hievable frequency is 40mhz. 3. maximum frequency of slave transmitter is determined by sum of tv(so) and tsu(mi) intervals which has to fit into sck level phase preceding the sck sampling edge.this value can be achieved when it communicates with a master having tsu(mi)=0 while signal duty(sck)=50%. table 76. spi dynamic characteristics (1) (continued) symbol parameter cond itions min typ max unit dlf 6&.,qsxw 166lqsxw w 68166 w f6&. w k166 &3+$ &32/ &3+$ &32/ w z6&.+ w z6&./ w 962 w k62 w u6&. w i6&. w glv62 w d62 0,62 287387 026, ,1387 06%287 %,7287 /6%287 w vx6, w k6, 06%,1 %,7,1 /6%,1
docid027589 rev 4 159/228 stm32f756xx electrical characteristics 196 figure 47. spi timing diagram - slave mode and cpha = 1 figure 48. spi timing diagram - master mode i 2 s interface characteristics unless otherwise specified, the parameters given in table 77 for the i 2 s interface are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd dl 6&.,qsxw &3+$ 026, ,1387 0,62 287 3 87 &3+$ 06 % 2 8 7 06% ,1 %, 7 28 7 /6% ,1 /6% 287 &32/ &32/ %,7 ,1 w 68166 w f6&. w k166 w d62 w z6&.+ w z6&./ w y62 w k62 w u6&. w i6&. w glv62 w vx6, w k6, 166lqsxw dlf 6&.2xwsxw &3+$ 026, 287387 0,62 ,13 87 &3+$ /6%287 /6%,1 &32/ &32/ % , 7287 166lqsxw w f6&. w z6&.+ w z6&./ w u6&. w i6&. w k0, +ljk 6&.2xwsxw &3+$ &3+$ &32/ &32/ w vx0, w y02 w k02 06%,1 %,7,1 06%287
electrical characteristics stm32f756xx 160/228 docid027589 rev 4 refer to section 5.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (ck, sd, ws). note: refer to rm0385 reference manual i2s section for more details on the sampling frequency (f s ). f mck , f ck , and d ck values reflect only the digital peripheral behavior. the values of these parameters might be slightly impacted by the source clock precision. d ck depends mainly on the value of odd bit. the digital contribution leads to a minimum value of (i2sdiv/(2*i2sdiv+odd) and a maximum va lue of (i2sdiv+odd) /(2*i2sdiv+odd). f s maximum value is supported for each mode/condition. table 77. i 2 s dynamic characteristics (1) symbol parameter conditions min max unit f mck i2s main clock output - 256x8k 256xfs (2) mhz f ck i2s clock frequency master data: 32 bits - 64xfs mhz slave data: 32 bits - 64xfs d ck i2s clock frequency duty cycle slave receiver 30 70 % t v(ws) ws valid time master mode - 5 ns t h(ws) ws hold time master mode 0 - t su(ws) ws setup time slave mode 5 - ns slave mode pcm short pulse mode (3) 3- t h(ws) ws hold time slave mode 0 - slave mode pcm short pulse mode (3) 2- t su(sd_mr) data input setup time master receiver 5 - t su(sd_sr) slave receiver 1 - t h(sd_mr) data input hold time master receiver 5 - t h(sd_sr) slave receiver 1.5 - t v(sd_st) data output valid time slave transmitter (after enable edge) - 16 t v(sd_mt) master transmitter (after enable edge) - 3.5 t h(sd_st) data output hold time slave transmitter (after enable edge) 5 - t h(sd_mt) master transmitter (after enable edge) 0 - 1. guaranteed by characterization results. 2. the maximum value of 256xfs is 45 mhz (apb1 maximum frequency). 3. measurement done with respect to i2s_ck rising edge.
docid027589 rev 4 161/228 stm32f756xx electrical characteristics 196 figure 49. i 2 s slave timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figure 50. i 2 s master timing diagram (philips protocol) (1) 1. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. &.,qsxw &32/ &32/ w f&. :6lqsxw 6' wudqvplw 6' uhfhlyh w z&.+ w z&./ w vx:6 w y6'b67 w k6'b67 w k:6 w vx6'b65 w k6'b65 06%uhfhlyh %lwquhfhlyh /6%uhfhlyh 06%wudqvplw %lwqwudqvplw /6%wudqvplw dle /6%uhfhlyh /6%wudqvplw #+output #0/, #0/, t c#+ 73output 3$ receive 3$ transmit t w#+( t w#+, t su3$?-2 t v3$?-4 t h3$?-4 t h73 t h3$?-2 -3"receive "itnreceive ,3"receive -3"transmit "itntransmit ,3"transmit aib t f#+ t r#+ t v73 ,3"receive ,3"transmit
electrical characteristics stm32f756xx 162/228 docid027589 rev 4 sai characteristics unless otherwise specified, the parameters given in table 78 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and vdd supply voltage conditions su mmarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c=30 pf ? measurement points are performed at cmos levels: 0.5v dd refer to section 5.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (sck,sd,ws). table 78. sai characteristics (1) symbol parameter conditions min max unit f mckl sai main clock output - 256 x 8k 256xfs (2) mhz f sck sai clock frequency master data: 32 bits - 128xfs mhz slave data: 32 bits - 128xfs d sck sai clock frequency duty cycle slave receiver 30 70 % t v(fs) fs valid time master mode 8 22 ns t su(fs) fs setup time slave mode 2 - t h(fs) fs hold time master mode 8 - slave mode 0 - t su(sd_mr) data input setup time master receiver 5 - t su(sd_sr) slave receiver 3 - t h(sd_mr) data input hold time master receiver 0 - t h(sd_sr) slave receiver 6 - t v(sd_st) t h(sd_st) data output valid time slave transmitter (after enable edge) -15 t v(sd_mt) master transmitter (after enable edge) -20 t h(sd_mt) data output hold time master transmitter (after enable edge) 7- 1. guaranteed by characterization results. 2. 256xfs maximum corresponds to 45 mhz (apb2 xaximum frequency)
docid027589 rev 4 163/228 stm32f756xx electrical characteristics 196 figure 51. sai master timing waveforms figure 52. sai slave timing waveforms -36 3!)?3#+?8 3!)?&3?8 output f 3#+ 3!)?3$?8 transmit t v&3 3lotn 3!)?3$?8 receive t h&3 3lotn t v3$?-4 t h3$?-4 3lotn t su3$?-2 t h3$?-2 -36 3!)?3#+?8 3!)?&3?8 input 3!)?3$?8 transmit t su&3 3lotn 3!)?3$?8 receive t w#+(?8 t h&3 3lotn t v3$?34 t h3$?34 3lotn t su3$?32 t w#+,?8 t h3$?32 f 3#+
electrical characteristics stm32f756xx 164/228 docid027589 rev 4 usb otg full speed (fs) characteristics this interface is present in both the usb otg hs and usb otg fs controllers. note: when vbus sensing feature is enabled, pa9 and pb13 should be left at their default state (floating input), not as alternate function. a typical 200 a current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on pa9 and pb13 when the feature is enabled. table 79. usb otg full speed startup time symbol parameter max unit t startup (1) 1. guaranteed by design. usb otg full speed transceiver startup time 1 s table 80. usb otg full speed dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v ddusb usb otg full speed transceiver operating voltage -3.0 (2) 2. the usb otg full speed transceiver functionality is ensured down to 2.7 v but not the full usb full speed electrical characteri stics which are degraded in the 2.7-to-3.0 v v ddusb voltage range. -3.6v v di (3) 3. guaranteed by design. differential input sensitivity i(usb_fs_dp/dm, usb_hs_dp/dm) 0.2 - - v v cm (3) differential common mode range includes v di range 0.8 - 2.5 v se (3) single ended receiver threshold -1.3-2.0 output levels v ol static output level low r l of 1.5 k to 3.6 v (4) 4. r l is the load connected on t he usb otg full speed drivers. --0.3 v v oh static output level high r l of 15 k to v ss (4) 2.8 - 3.6 r pd pa11, pa12, pb14, pb15 (usb_fs_dp/dm, usb_hs_dp/dm) v in = v dd 17 21 24 k pa9, pb13 (otg_fs_vbus, otg_hs_vbus) 0.65 1.1 2.0 r pu pa12, pb15 (usb_fs_dp, usb_hs_dp) v in = v ss 1.5 1.8 2.1 pa9, pb13 (otg_fs_vbus, otg_hs_vbus) v in = v ss 0.25 0.37 0.55
docid027589 rev 4 165/228 stm32f756xx electrical characteristics 196 figure 53. usb otg full speed timings: definition of data signal rise and fall time usb high speed (hs) characteristics unless otherwise specified, the parameters given in table 84 for ulpi are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 83 and v dd supply voltage cond itions summarized in table 82 , with the following configuration: ? output speed is set to ospeedry[1:0 ] = 11, unless otherwise specified ? capacitive load c = 20 pf, unless otherwise specified ? measurement points are done at cmos levels: 0.5v dd . refer to section 5.3.17: i/o port characteristics for more details on the input/output characteristics. table 81. usb otg full speed electrical characteristics (1) 1. guaranteed by design. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapter 7 (version 2.0). c l = 50 pf 420ns t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crosso ver voltage - 1.3 2.0 v z drv output driver impedance (3) 3. no external termination series resistors are requ ired on dp (d+) and dm (d-) pins since the matching impedance is included in the embedded driver. driving high or low 28 44 table 82. usb hs dc elect rical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd usb otg hs operating voltage 1.7 3.6 v dl w i 66 w u 9 &56 9 'liihuhqwldo gdwdolqhv &urvvryhu srlqwv
electrical characteristics stm32f756xx 166/228 docid027589 rev 4 figure 54. ulpi timing diagram table 83. usb hs cloc k timing parameters (1) 1. guaranteed by design. symbol parameter min typ max unit - f hclk value to guarantee proper operation of usb hs interface 30 - - mhz f start_8bit frequency (first transition) 8-bit 10% 54 60 66 mhz f steady frequency (steady state) 500 ppm 59.97 60 60.03 mhz d start_8bit duty cycle (first transition) 8-bit 10% 40 50 60 % d steady duty cycle (steady state) 500 ppm 49.975 50 50.025 % t steady time to reach the steady state frequency and duty cycle after the first transition --1.4ms t start_dev clock startup time after the de-assertion of suspendm peripheral - - 5.6 ms t start_host host - - - t prep phy preparation time after the first transition of the input clock ---s #lock #ontrol)n 5,0)?$)2 5,0)?.84 data)n bit #ontrolout 5,0)?340 dataout bit t $$ t $# t ($ t 3$ t (# t 3# aic t $#
docid027589 rev 4 167/228 stm32f756xx electrical characteristics 196 ethernet characteristics unless otherwise specified, the parameters given in table 85 , table 86 and table 87 for smi, rmii and mii are derived from tests performed under the ambient temperature, f hclk frequency summarized in table 17 and v dd supply voltage condit ions summarized in table 85 , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 20 pf ? measurement points are done at cmos levels: 0.5v dd . refer to section 5.3.17: i/o port characteristics for more details on the input/output characteristics. table 85 gives the list of ethernet mac signals for the smi (station management interface) and figure 55 shows the corresponding timing diagram. figure 55. ethernet smi timing diagram table 84. dynamic characteristics: usb ulpi (1) symbol parameter conditions min. typ. max. unit t sc control in (ulpi_dir, ulpi_nxt) setup time - 3 - - ns t hc control in (ulpi_dir, ulpi_nxt) hold time - 1 - - t sd data in setup time - 1.5 - - t hd data in hold time - 0.5 - - t dc /t dd data/control output delay 2.7 v < v dd < 3.6 v, c l = 20 pf and ospeedry[1:0] = 11 -5.59 -- 5.5 11.5 1.7 v < v dd < 3.6 v, c l = 15 pf and ospeedry[1:0] = 11 - 1. guaranteed by characterization results. 069 (7+b0'& (7+b0',22 (7+b0',2, w0'& wg0',2 wvx0',2 wk0',2
electrical characteristics stm32f756xx 168/228 docid027589 rev 4 table 86 gives the list of ethernet mac signals for the rmii and figure 56 shows the corresponding timing diagram. figure 56. ethernet rmii timing diagram table 85. dynamics characteristics: ethernet mac signals for smi (1) 1. guaranteed by characterization results. symbol parameter min typ max unit t mdc mdc cycle time(2.38 mhz) 400 400 403 ns t d(mdio) write data valid time 10 10.5 12.5 t su(mdio) read data setup time 12.5 - - t h(mdio) read data hold time 0 - - table 86. dynamics characteristi cs: ethernet mac signals for rmii (1) 1. guaranteed by characterization results. symbol parameter min typ max unit t su(rxd) receive data setup time 1 - - ns t ih(rxd) receive data hold time 1.5 - - t su(crs) carrier sense setup time 1 - - t ih(crs) carrier sense hold time 1 - - t d(txen) transmit enable valid delay time 5 6 10.5 t d(txd) transmit data valid delay time 5 6 12 50,,b5()b&/. 50,,b7;b(1 50,,b7;'>@ 50,,b5;'>@ 50,,b&56b' 9 w g7;(1 w g7;' w vx5;' w vx&56 w lk5;' w lk&56 dl
docid027589 rev 4 169/228 stm32f756xx electrical characteristics 196 table 87 gives the list of ethernet mac signals for mii and figure 56 shows the corresponding timing diagram. figure 57. ethernet mii timing diagram can (controller area network) interface refer to section 5.3.17: i/o port characteristics for more details on the input/output alternate function characteristics (canx_tx and canx_rx). table 87. dynamics characteristics: ethernet mac signals for mii (1) 1. guaranteed by characterization results. symbol parameter min typ max unit t su(rxd) receive data setup time 3 - - ns t ih(rxd) receive data hold time 1.5 - - t su(dv) data valid setup time 0 - - t ih(dv) data valid hold time 1.5 - - t su(er) error setup time 1.5 - - t ih(er) error hold time 0.5 - - t d(txen) transmit enable valid delay time 6.5 7 13.5 t d(txd) transmit data valid delay time 6.5 7 13.5 -))?28?#,+ -))?28$;= -))?28?$6 -))?28?%2 t d48%. t d48$ t su28$ t su%2 t su$6 t ih28$ t ih%2 t ih$6 ai -))?48?#,+ -))?48?%. -))?48$;=
electrical characteristics stm32f756xx 170/228 docid027589 rev 4 5.3.27 fmc characteristics unless otherwise specified, the parameters given in table 88 to table 101 for the fmc interface are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? measurement points are done at cmos levels: 0.5v dd refer to section 5.3.17: i/o port characteristics for more details on the input/output characteristics. asynchronous waveforms and timings figure 58 through figure 61 represent asynchronous waveforms and table 88 through table 95 provide the corresponding ti mings. the results shown in these tables are obtained with the following fm c configuration: ? addresssetuptime = 0x1 ? addressholdtime = 0x1 ? datasetuptime = 0x1 (except for asynchronous nwait mode , datasetuptime = 0x5) ? busturnaroundduration = 0x0 ? capcitive load cl = 30 pf in all timing tables, the t hclk is the hclk clock period
docid027589 rev 4 171/228 stm32f756xx electrical characteristics 196 figure 58. asynchronous non-multiplexed sram/psram/nor read waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. $ata &-#?.% &-#?.",;= &-#?$;= t v",?.% t h$ata?.% &-#?./% !ddress &-#?!;= t v!?.% &-#?.7% t su$ata?.% t w.% -36 w./% t t v./%?.% t h.%?./% t h$ata?./% t h!?./% t h",?./% t su$ata?./% &-#?.!$6 t v.!$6?.% t w.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
electrical characteristics stm32f756xx 172/228 docid027589 rev 4 table 88. asynchronous non-multiplexed sram/psram/nor read timings (1) 1. c l = 30 pf. symbol parameter min max unit t w(ne) fmc_ne low time 2t hclk ? 0.5 2 t hclk +1.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 0 1 t w(noe) fmc_noe low time 2t hclk ? 12t hclk + 1 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 0.5 t h(a_noe) address hold time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0.5 t h(bl_noe) fmc_bl hold time after fmc_noe high 0 - t su(data_ne) data to fmc_nex high setup time t hclk - 2 - t su(data_noe) data to fmc_noex high setup time t hclk -2 - t h(data_noe) data hold time after fmc_noe high 0 - t h(data_ne) data hold time after fmc_nex high 0 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk +1 table 89. asynchronous non-multiplexed sram/psram/nor read - nwait timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 7t hclk ? 17t hclk ns t w(noe) fmc_nwe low time 5t hclk ? 15t hclk +1 t w(nwait) fmc_nwait low time t hclk ? 0.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 -
docid027589 rev 4 173/228 stm32f756xx electrical characteristics 196 figure 59. asynchronous non-multiplexed sram/psram/nor write waveforms 1. mode 2/b, c and d only. in mode 1, fmc_nadv is not used. table 90. asynchronous non-multiplexed sram/psram/nor write timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk ? 0.5 3t hclk +1.5 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 0.5 t hclk + 1 t w(nwe) fmc_nwe low time t hclk ? 0.5 t hclk + 1 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk ? 0.5 - t v(a_ne) fmc_nex low to fmc_a valid - 0 t h(a_nwe) address hold time after fmc_nwe high t hclk ? 0.5 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0 t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk ? 0.5 - t v(data_ne) data to fmc_nex low to data valid - t hclk + 3 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - t v(nadv_ne) fmc_nex low to fmc_nadv low - 0 t w(nadv) fmc_nadv low time - t hclk + 0.5 .", $ata &-#?.%x &-#?.",;= &-#?$;= t v",?.% t h$ata?.7% &-#?./% !ddress &-#?!;= t v!?.% t w.7% &-#?.7% t v.7%?.% t h.%?.7% th!?.7% t h",?.7% t v$ata?.% t w.% -36 &-#?.!$6 t v.!$6?.% t w.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
electrical characteristics stm32f756xx 174/228 docid027589 rev 4 figure 60. asynchronous multiplexed psram/nor read waveforms table 91. asynchronous non-multiplexed sram/psram/nor write - nwait timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk ? 0.5 8t hclk +1.5 ns t w(nwe) fmc_nwe low time 6t hclk ? 0.5 6t hclk +1 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk ? 1- t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +2 - .", $ata &-#? .",;= &-#? !$;= t v",?.% t h$ata?.% !ddress &-#? !;= t v!?.% &-#?.7% t v!?.% -36 !ddress &-#?.!$6 t v.!$6?.% t w.!$6 t su$ata?.% t h!$?.!$6 &-#? .% &-#?./% t w.% t w./% t v./%?.% t h.%?./% t h!?./% t h",?./% t su$ata?./% t h$ata?./% &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
docid027589 rev 4 175/228 stm32f756xx electrical characteristics 196 table 92. asynchronous multiplexed psram/nor read timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 3t hclk ? 0.5 3t hclk +1.5 ns t v(noe_ne) fmc_nex low to fmc_noe low 2t hclk ? 12t hclk +0.5 t tw(noe) fmc_noe low time t hclk ? 0.5 t hclk +0.5 t h(ne_noe) fmc_noe high to fmc_ne high hold time 0 - t v(a_ne) fmc_nex low to fmc_a valid - 0.5 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 0.5 t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk +1.5 t h(ad_nadv) fmc_ad(address) valid hold time after fmc_nadv high) 0 - t h(a_noe) address hold time after fmc_noe high t hclk ? 0.5 - t h(bl_noe) fmc_bl time after fmc_noe high 0 - t v(bl_ne) fmc_nex low to fmc_bl valid - 0.5 t su(data_ne) data to fmc_nex high setup time t hclk ? 2 - t su(data_noe) data to fmc_noe high setup time t hclk ? 2 - t h(data_ne) data hold time after fmc_nex high 0 - t h(data_noe) data hold time after fmc_noe high 0 - table 93. asynchronous multiplexed psram/nor read-nwait timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 8t hclk ? 18t hclk +2 ns t w(noe) fmc_nwe low time 5t hclk ? 15t hclk +1 t su(nwait_ne) fmc_nwait valid before fmc_nex high 5t hclk +1.5 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk +1 -
electrical characteristics stm32f756xx 176/228 docid027589 rev 4 figure 61. asynchronous multip lexed psram/nor write waveforms table 94. asynchronous multiplexed psram/nor write timings (1) symbol parameter min max unit t w(ne) fmc_ne low time 4t hclk ? 0.5 4t hclk +1.5 ns t v(nwe_ne) fmc_nex low to fmc_nwe low t hclk ? 1t hclk +0.5 t w(nwe) fmc_nwe low time 2t hclk ? 0.5 2t hclk +0.5 t h(ne_nwe) fmc_nwe high to fmc_ne high hold time t hclk - t v(a_ne) fmc_nex low to fmc_a valid - 0 t v(nadv_ne) fmc_nex low to fmc_nadv low 0 0.5 t w(nadv) fmc_nadv low time t hclk ? 0.5 t hclk + 1.5 t h(ad_nadv) fmc_ad(adress) valid hold time after fmc_nadv high) t hclk ? 2- t h(a_nwe) address hold time after fmc_nwe high t hclk - t h(bl_nwe) fmc_bl hold time after fmc_nwe high t hclk ? 2- t v(bl_ne) fmc_nex low to fmc_bl valid - 0 t v(data_nadv) fmc_nadv high to data valid - t hclk +2 t h(data_nwe) data hold time after fmc_nwe high t hclk +0.5 - .", $ata &-#? .%x &-#? .",;= &-#? !$;= t v",?.% t h$ata?.7% &-#?./% !ddress &-#? !;= t v!?.% t w.7% &-#?.7% t v.7%?.% t h.%?.7% t h!?.7% t h",?.7% t v!?.% t w.% -36 !ddress &-#?.!$6 t v.!$6?.% t w.!$6 t v$ata?.!$6 t h!$?.!$6 &-#?.7!)4 tsu.7!)4?.% th.%?.7!)4
docid027589 rev 4 177/228 stm32f756xx electrical characteristics 196 synchronous waveforms and timings figure 62 through figure 65 represent synchronous waveforms and table 96 through table 99 provide the corresponding ti mings. the results shown in these tables are obtained with the following fm c configuration: ? burstaccessmode = fmc_ burstaccessmode_enable; ? memorytype = fmc_memorytype_cram; ? writeburst = fmc_writeburst_enable; ? clkdivision = 1; ? datalatency = 1 for nor flash; datalatency = 0 for psram ? cl = 30 pf on data and address lines. cl = 10 pf on fmc_clk unless otherwise specified. in all timing tables, the t hclk is the hclk clock period. ?for 2.7 v v dd 3.6 v, maximum fmc_clk = 108 mhz at cl=20 pf or 90 mhz at cl=30 pf (on fmc_clk). ?for 1.71 v v dd <2.7 v, maximum fmc_clk = 70 mhz at cl=10 pf (on fmc_clk). 1. guaranteed by characterization results. table 95. asynchronous multiplexed psram/nor write-nwait timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(ne) fmc_ne low time 9t hclk 9t hclk +1.5 ns t w(nwe) fmc_nwe low time 7t hclk ?0.5 7t hclk +0.5 t su(nwait_ne) fmc_nwait valid before fmc_nex high 6t hclk +2 - t h(ne_nwait) fmc_nex hold time after fmc_nwait invalid 4t hclk ?1 -
electrical characteristics stm32f756xx 178/228 docid027589 rev 4 figure 62. synchronous multiplexed nor/psram read timings &-#?#,+ &-#?.%x &-#?.!$6 &-#?!;= &-#?./% &-#?!$;= !$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, td#,+( .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( td#,+( !)6 t d#,+, ./%, td#,+( ./%( t d#,+, !$6 t d#,+, !$)6 t su!$6 #,+( t h#,+( !$6 t su!$6 #,+( t h#,+( !$6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 -36
docid027589 rev 4 179/228 stm32f756xx electrical characteristics 196 table 96. synchronous multiple xed nor/psram read timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 0.5 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2 t d(clkh_nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 1.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 2 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk ? 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t su(adv-clkh) fmc_a/d[15:0] valid data before fmc_clk high 1.5 - t h(clkh-adv) fmc_a/d[15:0] valid data after fmc_clk high 1 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 -
electrical characteristics stm32f756xx 180/228 docid027589 rev 4 figure 63. synchronous multiplexed psram write timings &-#?#,+ &-#?.%x &-#?.!$6 &-#?!;= &-#?.7% &-#?!$;= !$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency "53452. t d#,+, .%x, t d#,+( .%x( t d#,+, .!$6, t d#,+, !6 t d#,+, .!$6( t d#,+( !)6 t d#,+( .7%( t d#,+, .7%, t d#,+( .",( t d#,+, !$6 t d#,+, !$)6 t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 -36 t d#,+, $ata &-#?.",
docid027589 rev 4 181/228 stm32f756xx electrical characteristics 196 table 97. synchronous multiplexed psram write timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 0.5 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 1.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 1.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 1.5 t (clkh-nweh) fmc_clk high to fmc_nwe high t hclk ? 0.5 - t d(clkl-adv) fmc_clk low to fmc_ad[15:0] valid - 3 t d(clkl-adiv) fmc_clk low to fmc_ad[15:0] invalid 0 - t d(clkl-data) fmc_a/d[15:0] valid data after fmc_clk low - 3.5 t d(clkl-nbll) fmc_clk low to fmc_nbl low 1 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk +0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 -
electrical characteristics stm32f756xx 182/228 docid027589 rev 4 figure 64. synchronous non-multiplexed nor/psram read timings table 98. synchronous non-multiplexed nor/psram read timings (1) symbol parameter min max unit t w(clk) fmc_clk period 2t hclk ? 1 - ns t (clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2.5 t d(clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 0 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) t hclk - t d(clkl-noel) fmc_clk low to fmc_noe low - 2 t d(clkh-noeh) fmc_clk high to fmc_noe high t hclk +0.5 - t su(dv-clkh) fmc_d[15:0] valid data before fmc_clk high 1.5 - t h(clkh-dv) fmc_d[15:0] valid data after fmc_clk high 1 - t (nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 - &-#?#,+ &-#?.%x &-#?!;= &-#?./% &-#?$;= $ $ &-#?.7!)4 7!)4#&'b 7!)40/,b &-#?.7!)4 7!)4#&'b 7!)40/,b t w#,+ t w#,+ $atalatency t d#,+, .%x, t d#,+( .%x( t d#,+, !6 t d#,+( !)6 t d#,+, ./%, t d#,+( ./%( t su$6 #,+( t h#,+( $6 t su$6 #,+( t h#,+( $6 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 t su.7!)46 #,+( t h#,+( .7!)46 -36 &-#?.!$6 t d#,+, .!$6, t d#,+, .!$6(
docid027589 rev 4 183/228 stm32f756xx electrical characteristics 196 figure 65. synchronous non-multi plexed psram write timings 1. guaranteed by characterization results. -36 &-#?#,+ &-#?.%x &-#?!;= &-#?.7% &-#?$;= $ $ &-#?.7!)4 7!)4#&'b7!)40/,b t w#,+ t w#,+ $atalatency t d#,+, .%x, t d#,+( .%x( t d#,+, !6 t d#,+( !)6 t d#,+( .7%( t d#,+, .7%, t d#,+, $ata t su.7!)46 #,+( t h#,+( .7!)46 &-#?.!$6 t d#,+, .!$6, t d#,+, .!$6( t d#,+, $ata &-#?.", t d#,+( .",(
electrical characteristics stm32f756xx 184/228 docid027589 rev 4 nand controller waveforms and timings figure 66 through figure 69 represent synchronous waveforms, and table 100 and table 101 provide the corresponding timings. the results shown in this table are obtained with the following fm c configuration: ? com.fmc_setuptime = 0x01; ? com.fmc_waitsetuptime = 0x03; ? com.fmc_holdsetuptime = 0x02; ? com.fmc_hizsetuptime = 0x01; ? att.fmc_setuptime = 0x01; ? att.fmc_waitsetuptime = 0x03; ? att.fmc_holdsetuptime = 0x02; ? att.fmc_hizsetuptime = 0x01; ? bank = fmc_bank_nand; ? memorydatawidth = fmc_memorydatawidth_16b; ? ecc = fmc_ecc_enable; ? eccpagesize = fmc_eccpagesize_512bytes; ? tclrsetuptime = 0; ? tarsetuptime = 0. in all timing tables, the t hclk is the hclk clock period. table 99. synchronous non-multiplexed psram write timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t (clk) fmc_clk period 2t hclk ? 1 - ns t d(clkl-nexl) fmc_clk low to fmc_nex low (x=0..2) - 2.5 t (clkh-nexh) fmc_clk high to fmc_nex high (x= 0?2) t hclk +0.5 - t d(clkl-nadvl) fmc_clk low to fmc_nadv low - 1.5 t d(clkl-nadvh) fmc_clk low to fmc_nadv high 0 - t d(clkl-av) fmc_clk low to fmc_ax valid (x=16?25) - 2.5 t d(clkh-aiv) fmc_clk high to fmc_ax invalid (x=16?25) 0 - t d(clkl-nwel) fmc_clk low to fmc_nwe low - 1.5 t d(clkh-nweh) fmc_clk high to fmc_nwe high t hclk +1 - t d(clkl-data) fmc_d[15:0] valid data after fmc_clk low - 3 t d(clkl-nbll) fmc_clk low to fmc_nbl low 1.5 - t d(clkh-nblh) fmc_clk high to fmc_nbl high t hclk +0.5 - t su(nwait-clkh) fmc_nwait valid before fmc_clk high 2 - t h(clkh-nwait) fmc_nwait valid after fmc_clk high 3.5 -
docid027589 rev 4 185/228 stm32f756xx electrical characteristics 196 figure 66. nand controller waveforms for read access figure 67. nand controller waveforms for write access figure 68. nand controller waveforms for common memory read access &-#?.7% &-#?./%.2% &-#?$;= t su$ ./% t h./% $ -36 !,%&-#?! #,%&-#?! &-#?.#%x t d!,% ./% th./% !,% -36 t h.7% $ t v.7% $ &-#?.7% &-#?./%.2% &-#?$;= !,%&-#?! #,%&-#?! &-#?.#%x t d!,% .7% t h.7% !,% -36 &-#?.7% &-#?./% &-#?$;= t w./% t su$ ./% t h./% $ !,%&-#?! #,%&-#?! &-#?.#%x t d!,% ./% t h./% !,%
electrical characteristics stm32f756xx 186/228 docid027589 rev 4 figure 69. nand controller wavefo rms for common memory write access table 100. switching characteristics for nand flash read cycles (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(n0e) fmc_noe low width 4t hclk ? 0.5 4t hclk ns t su(d-noe) fmc_d[15-0] valid data before fmc_noe high 13 - t h(noe-d) fmc_d[15-0] valid data after fmc_noe high 3 - t d(ale-noe) fmc_ale valid before fmc_noe low - 3t hclk ? 0.5 t h(noe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 2- table 101. switching characterist ics for nand flas h write cycles (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(nwe) fmc_nwe low width 4t hclk ? 0.5 4t hclk ns t v(nwe-d) fmc_nwe low to fmc_d[15-0] valid 0 - t h(nwe-d) fmc_nwe high to fmc_d[15-0] invalid 3t hclk ? 1- t d(d-nwe) fmc_d[15-0] valid before fmc_nwe high 5t hclk ? 3- t d(ale-nwe) fmc_ale valid before fmc_nwe low - 3t hclk ? 0.5 t h(nwe-ale) fmc_nwe high to fmc_ale invalid 3t hclk ? 2- -36 t w.7% t h.7% $ t v.7% $ &-#?.7% &-#?. /% &-#?$;= t d$ .7% !,%&-#?! #,%&-#?! &-#?.#%x t d!,% ./% t h./% !,%
docid027589 rev 4 187/228 stm32f756xx electrical characteristics 196 sdram waveforms and timings ? cl = 30 pf on data and address lines. cl = 10 pf on fmc_sdclk unless otherwise specified. in all timing tables, the t hclk is the hclk clock period. ? for 3.0 v v dd 3.6 v, maximum fmc_sdclk= 100 mhz at cl=20 pf (on fmc_sdclk). ? for 2.7 v v dd 3.6 v, maximum fmc_sdclk = 90 mhz at cl=30 pf (on fmc_sdclk). ? for 1.71 v v dd <1.9 v, maximum fmc_sdclk = 70 mhz at cl=10 pf (on fmc_sdclk). figure 70. sdram read access waveforms (cl = 1) -36 2own #ol &-#?3$#,+ &-#?! >@ &-#?3$.2!3 &-#?3$.#!3 &-#?3$.7% &-#?$;= &-#?3$.%;= td3$#,+,?!dd2 td3$#,+,?!dd# th3$#,+,?!dd2 th3$#,+,?!dd# td3$#,+,?3.$% tsu3$#,+(?$ata th3$#,+(?$ata #ol #oli #oln $ata $atai $atan $ata th3$#,+,?3.$% td3$#,+,?.2!3 td3$#,+,?.#!3 th3$#,+,?.#!3 th3$#,+,?.2!3
electrical characteristics stm32f756xx 188/228 docid027589 rev 4 table 102. sdram read timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t su(sdclkh _data) data input setup time 3.5 - t h(sdclkh_data) data input hold time 1.5 - t d(sdclkl_add) address valid time - 4 t d(sdclkl- sdne) chip select valid time - 0.5 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 0.5 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t h(sdclkl_sdncas) sdncas hold time 0 - table 103. lpsdr sdram read timings (1) 1. guaranteed by characterization results. symbol paramete r min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t su(sdclkh_data) data input setup time 3 - t h(sdclkh_data) data input hold time 1.5 - t d(sdclkl_add) address valid time - 3.5 t d(sdclkl_sdne) chip select valid time - 0.5 t h(sdclkl_sdne) chip select hold time 0 - t d(sdclkl_sdnras sdnras valid time - 0.5 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t h(sdclkl_sdncas) sdncas hold time 0 -
docid027589 rev 4 189/228 stm32f756xx electrical characteristics 196 figure 71. sdram write access waveforms table 104. sdram write timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t d(sdclkl _data ) data output valid time - 2 t h(sdclkl _data) data output hold time 0.5 - t d(sdclkl_add) address valid time - 4 t d(sdclkl_sdnwe) sdnwe valid time - 0.5 t h(sdclkl_sdnwe) sdnwe hold time 0 - t d(sdclkl_ sdne) chip select valid time - 0.5 t h(sdclkl-_sdne) chip select hold time 0 - t d(sdclkl_sdnras) sdnras valid time - 0.5 t h(sdclkl_sdnras) sdnras hold time 0 - t d(sdclkl_sdncas) sdncas valid time - 0.5 t d(sdclkl_sdncas) sdncas hold time 0 - -36 2own #ol &-#?3$#,+ &-#?! >@ &-#?3$.2!3 &-#?3$.#!3 &-#?3$.7% &-#?$;= &-#?3$.%;= td3$#,+,?!dd2 td3$#,+,?!dd# th3$#,+,?!dd2 th3$#,+,?!dd# td3$#,+,?3.$% td3$#,+,?$ata th3$#,+,?$ata #ol #oli #oln $ata $atai $atan $ata th3$#,+,?3.$% td3$#,+,?.2!3 td3$#,+,?.#!3 th3$#,+,?.#!3 th3$#,+,?.2!3 td3$#,+,?.7% th3$#,+,?.7% &-#?.",;= td3$#,+,?.",
electrical characteristics stm32f756xx 190/228 docid027589 rev 4 5.3.28 quad-spi in terface characteristics unless otherwise specified, the parameters given in table 106 and table 107 for quad-spi are derived from tests performed under the ambient temperature, f ahb frequency and v dd supply voltage condit ions summarized in table 17: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 20 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 5.3.17: i/o port characteristics for more details on the input/output alternate function characteristics. table 105. lpsdr sdram write timings (1) 1. guaranteed by characterization results. symbol parameter min max unit t w(sdclk) fmc_sdclk period 2t hclk ? 0.5 2t hclk +0.5 ns t d(sdclkl _data ) data output valid time - 4 t h(sdclkl _data) data output hold time 0 - t d(sdclkl_add) address valid time - 3.5 t d(sdclkl-sdnwe) sdnwe valid time - 0.5 t h(sdclkl-sdnwe) sdnwe hold time 0 - t d(sdclkl- sdne) chip select valid time - 0.5 t h(sdclkl- sdne) chip select hold time 0 - t d(sdclkl-sdnras) sdnras valid time - 0.5 t h(sdclkl-sdnras) sdnras hold time 0 - t d(sdclkl-sdncas) sdncas valid time - 0.5 t d(sdclkl-sdncas) sdncas hold time 0 - table 106. quad-spi characteristics in sdr mode (1) symbol parameter conditions min typ max unit fck1/t(ck) quad-spi clock frequency 2.7 v v dd <3.6 v cl=20 pf - - 108 mhz 1.71 v docid027589 rev 4 191/228 stm32f756xx electrical characteristics 196 tw(ckh) quad-spi clock high and low time - t(ck)/2 -1 - t(ck)/2 ns tw(ckl) t(ck)/2 - t(ck)/2+1 ts(in) data input setup time - 1-- th(in) data input hold time 3 - - tv(out) data output valid time 2.7 v electrical characteristics stm32f756xx 192/228 docid027589 rev 4 figure 72. quad-spi timing diagram - sdr mode figure 73. quad-spi ti ming diagram - ddr mode 5.3.29 camera interface (d cmi) timing specifications unless otherwise specified, the parameters given in table 108 for dcmi are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage summarized in table 17 , with the following configuration: ? dcmi_pixclk polarity: falling ? dcmi_vsync and dcmi_hsync polarity: high ? data formats: 14 bits 06y9 'dwdrxwsxw ' ' ' &orfn 'dwdlqsxw ' ' ' w &. w z&.+ w z&./ w u&. w i&. w v,1 w k,1 w y287 w k287 06y9 'dwdrxwsxw ' ' ' &orfn 'dwdlqsxw ' ' ' w &. w z&.+ w z&./ w u&. w i&. w vi,1 w ki,1 w yi287 w ku287 ' ' ' ' ' ' w yu287 w ki287 w vu,1 w ku,1 table 108. dcmi characteristics (1) 1. guaranteed by characterization results. symbol parameter min max unit - frequency ratio dcmi_pixclk/f hclk -0.4 dcmi_pixclk pixel clock input - 54 mhz d pixel pixel clock input duty cycle 30 70 % t su(data) data input setup time 3.5 - ns t h(data) data input hold time 0 - t su(hsync) t su(vsync) dcmi_hsync/dcmi_vsync input setup time 2.5 - t h(hsync) t h(vsync) dcmi_hsync/dcmi_vsync input hold time 0 -
docid027589 rev 4 193/228 stm32f756xx electrical characteristics 196 figure 74. dcmi timing diagram 5.3.30 lcd-tft controller (ltdc) characteristics unless otherwise specified, the parameters given in table 109 for lcd-tft are derived from tests performed under the ambient temperature, f hclk frequency and v dd supply voltage summarized in table 17 , with the following configuration: ? lcd_clk polarity: high ? lcd_de polarity : low ? lcd_vsync and lcd_hsync polarity: high ? pixel formats: 24 bits 069 '&0,b3,;&/. w vx96<1& w vx+6<1& '&0,b+6<1& '&0,b96<1& '$7$>@ '&0,b3,;&/. w k+6<1& w k+6<1& w vx'$7$ w k'$7$ table 109. ltdc characteristics (1) 1. guaranteed by characterization results. symbol paramete rminmaxunit f clk ltdc clock output frequency - 45 mhz d clk ltdc clock output duty cycle 45 55 % t w(clkh) t w(clkl) clock high time, low time tw(clk)/2 ? 0.5 tw(clk)/2+0.5 ns t v(data) data output valid time - 6 t h(data) data output hold time 2 - t v(hsync) hsync/vsync/de output valid time -3 t v(vsync) t v(de) t h(hsync) hsync/vsync/de output hold time 0.5 - t h(vsync) th(de)
electrical characteristics stm32f756xx 194/228 docid027589 rev 4 figure 75. lcd-tft horizontal timing diagram figure 76. lcd-tft vertical timing diagram 069 /&'b&/. wy+6<1& /&'b+6<1& /&'b'( /&'b5>@ /&'b*>@ /&'b%>@ w&/. /&'b96<1& wy+6<1& wy'( wk'( 1jyfm 1jyfm wy'$7$ wk'$7$ 1jyfm / +6<1& zlgwk +rul]rqwdo edfnsrufk $fwlyhzlgwk +rul]rqwdo edfnsrufk 2qholqh 069 /&'b&/. wy96<1& /&'b5>@ /&'b*>@ /&'b%>@ w&/. /&'b96<1& wy96<1& -linesdata 96<1& zlgwk 9huwlfdo edfnsrufk $fwlyhzlgwk 9huwlfdo edfnsrufk 2qhiudph
docid027589 rev 4 195/228 stm32f756xx electrical characteristics 196 5.3.31 sd/sdio mmc card host in terface (sdmmc) characteristics unless otherwise specified, the parameters given in table 110 for the sdio/mmc interface are derived from tests performed under the ambient temperature, f pclk2 frequency and v dd supply voltage conditions summarized in table 17 , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5v dd refer to section 5.3.17: i/o port characteristics for more details on the input/output characteristics. figure 77. sdio high-speed mode figure 78. sd default mode t 7#+( #+ $#-$ output $#-$ input t # t 7#+, t /6 t /( t )35 t )( t f t r ai ai #+ $#-$ output t /6$ t /($
electrical characteristics stm32f756xx 196/228 docid027589 rev 4 table 110. dynamic characteristic s: sd / mmc characteristics, v dd =2.7v to 3.6v (1) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdmmc_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time fpp =50 mhz 9.5 10.5 - ns t w(ckh) clock high time fpp =50 mhz 8.5 9.5 - cmd, d inputs (referenced to ck) in mmc and sd hs mode t isu input setup time hs fpp =50 mhz 2.5 - - ns t ih input hold time hs fpp =50 mhz 3 - - cmd, d outputs (referenced to ck) in mmc and sd hs mode t ov output valid time hs fpp =50 mhz - 11.5 12 ns t oh output hold time hs fpp =50 mhz 10.5 - - cmd, d inputs (referenced to ck) in sd default mode tisud input setup ti me sd fpp =25 mhz 2- - ns tihd input hold time sd fpp =25 mhz 4- - cmd, d outputs (referenced to ck) in sd default mode tovd output valid default time sd fpp =25 mhz -1.52 ns tohd output hold default time sd fpp =25 mhz 0.5 - - 1. guaranteed by characterization results,. table 111. dynamic characteristics: emmc characteristics, v dd =1.71v to 1.9v (1)(2) symbol parameter conditions min typ max unit f pp clock frequency in data transfer mode - 0 - 50 mhz - sdmmc_ck/fpclk2 frequency ratio - - - 8/3 - t w(ckl) clock low time fpp =50 mhz 9.5 10.5 - ns t w(ckh) clock high time fpp =50 mhz 8.5 9.5 - cmd, d inputs (referenced to ck) in emmc mode t isu input setup time hs fpp =50 mhz 0.5 - - ns t ih input hold time hs fpp =50 mhz 3.5 - - cmd, d outputs (reference d to ck) in emmc mode t ov output valid time hs fpp =50 mhz - 12 12.5 ns t oh output hold time hs fpp =50 mhz 11 - - 1. guaranteed by characterization results. 2. cload = 20 pf.
docid027589 rev 4 197/228 stm32f756xx package information 227 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 6.1 lqfp100, 14 x 14 mm lo w-profile quad flat package information figure 79. lqfp100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. drawing is not to scale. e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).'0,!.% $ $ $ % % % + ccc # # ,?-%?6 ! ! ! , , c b !
package information stm32f756xx 198/228 docid027589 rev 4 table 112. lqpf100, 14 x 14 mm 100-pin lo w-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031
docid027589 rev 4 199/228 stm32f756xx package information 227 figure 80. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. marking of engineering samples the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 81. lqfp100, 14 x 14 mm, 100-pin low-profile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. aic 069 45.' 7(5 3 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh 88 : 'dwhfrgh 3lqlghqwlilhu
package information stm32f756xx 200/228 docid027589 rev 4 6.2 tfbga100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package information figure 82. tfbga100, 8 8 0.8 mm thin fine-pitch ball grid array package outline 1. drawing is not to scale. table 113. tfbga100, 8 x 8 0.8 mm thin fine-pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.100 - - 0.0433 a1 0.150 - - 0.0059 - - a2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 6($7,1* 3/$1( . - + * ) ( ' & % $ $ $ $ & ggg & %$//6 e hhh iii &$% & ' ( ) h % * h $edoo lghqwlilhu $edoo lqgh[ duhd $ $4b0(b9 ' (
docid027589 rev 4 201/228 stm32f756xx package information 227 figure 83. tfbga100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array package recommended footprint 1. dimensions are expr essed in millimeters. d 7.850 8.000 8.150 0.3091 0.3150 0.3209 d1 - 7.200 - 0.2835 - e 7.850 8.000 8.150 0.3091 0.3150 0.3209 e1 - 7.200 - - 0.2835 - e - 0.800 - - 0.0315 - f - 0.400 - - 0.0157 - g - 0.400 - - 0.0157 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 113. tfbga100, 8 x 8 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 'sdg 'vp
package information stm32f756xx 202/228 docid027589 rev 4 marking of engineering samples the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 84. tfbga100, 8 8 0.8mm thin fine-pitch ball grid array package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 114. tfbga100 recommended pcb design rules (0.8 mm pitch bga) dimension recommended values pitch 0.8 dpad 0.400 mm dsm 0.470 mm typ (depends on the soldermask registration tolerance) stencil opening 0.400 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.120 mm 069 %doo$ lghqwlilhu 'dwhfrgh :88 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 3 45.' 7()
docid027589 rev 4 203/228 stm32f756xx package information 227 6.3 wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package information figure 85. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package outline 1. drawing is not to scale. table 115. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - $b0(b9 h ) * h h %rwwrpylhz %xpsvlgh h $edooorfdwlrq ' $rulhqwdwlrq uhihuhqfh 7rsylhz :dihuedfnvlgh 'hwdlo$ $ $ 6lghylhz $ ( 'hwdlo$ 5rwdwhg? %xps 6hdwlqj sodqh e $ $ ddd fff ggg = = ; < eee hhh
package information stm32f756xx 204/228 docid027589 rev 4 figure 86. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package recommended footprint a2 - 0.380 - - 0.0150 - a3 (2) - 0.025 - - 0.0010 - b (3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 4.504 4.539 4.574 0.1773 0.1787 0.1801 e 5.814 5.849 5.884 0.2289 0.2303 0.2317 e - 0.400 - - 0.0157 - e1 - 4.000 - - 0.1575 - e2 - 4.800 - - 0.1890 - f - 0.2695 - - 0.0106 - g - 0.5245 - - 0.0206 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1. values in inches are converted from mm and rounded to 4 decimal digits. 2. back side coating. 3. dimension is measured at the maximum bum p diameter parallel to primary datum z. table 115. wlcsp143, 4.539x 5.849 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max $b)3b9 'sdg 'vp
docid027589 rev 4 205/228 stm32f756xx package information 227 marking of engineering samples the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 87. wlcsp143, 0.4 mm pitch wafer level chip scale package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. table 116. wlcsp143 recommended pcb design rules dimension recommended values pitch 0.4 dpad 0.225 mm dsm 0.290 mm typ. (depends on the soldermask registration tolerance) stencil opening 0.250 mm stencil thickness 0.100 mm 069 88 %doo$ lghqwlilhu 45.';(: : 'dwhfrgh 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 3
package information stm32f756xx 206/228 docid027589 rev 4 6.4 lqfp144, 20 x 20 mm lo w-profile quad flat package information figure 88. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. drawing is not to scale. table 117. lqfp144, 20 x 20 mm, 144- pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 21.800 22.000 22.200 0.8583 0.8661 0.874 e )$%.4)&)#!4)/. 0). '!5'%0,!.% mm 3%!4).' 0,!.% $ $ $ % % % + ccc # # !?-%?6 ! ! ! , , c b !
docid027589 rev 4 207/228 stm32f756xx package information 227 figure 89. lqfp144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. d1 19.800 20.000 20.200 0.7795 0.7874 0.7953 d3 - 17.500 - - 0.689 - e 21.800 22.000 22.200 0.8583 0.8661 0.8740 e1 19.800 20.000 20.200 0.7795 0.7874 0.7953 e3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 117. lqfp144, 20 x 20 mm, 144- pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max dlh
package information stm32f756xx 208/228 docid027589 rev 4 marking of engineering samples the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 90. lqfp144, 20 x 20mm, 144-pin low-profile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. -36 3lq lghqwlilhu 3 5hylvlrqfrgh ';(5 3urgxfwlghqwlilfdwlrq 'dwhfrgh :88
docid027589 rev 4 209/228 stm32f756xx package information 227 6.5 lqfp176, 24 x 24 mm lo w-profile quad flat package information figure 91. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package outline 1. drawing is not to scale. table 118. lqfp176, 24 x 24 mm, 176- pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 - 1.450 0.0531 - 0.0060 b 0.170 - 0.270 0.0067 - 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 23.900 - 24.100 0.9409 - 0.9488 4?-%?6 ! ! e % (% $ ($ :$ :% b mm gaugeplane ! , , k c )$%.4)&)#!4)/. 0). 3eatingplane # !
package information stm32f756xx 210/228 docid027589 rev 4 e 23.900 - 24.100 0.9409 - 0.9488 e - 0.500 - - 0.0197 - hd 25.900 - 26.100 1.0200 - 1.0276 he 25.900 - 26.100 1.0200 - 1.0276 l 0.450 - 0.750 0.0177 - 0.0295 l1 - 1.000 - - 0.0394 - zd - 1.250 - - 0.0492 - ze - 1.250 - - 0.0492 - ccc - - 0.080 - - 0.0031 k0 -7 0 -7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 118. lqfp176, 24 x 24 mm, 176- pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
docid027589 rev 4 211/228 stm32f756xx package information 227 figure 92. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. 4?&0?6
package information stm32f756xx 212/228 docid027589 rev 4 marking of engineering samples the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 93. lqfp176, 24 x 24 mm, 176-pin low-profile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 88 : 3lq lghqwlilhu 45.'*(5 3 'dwhfrgh 3urgxfwlghqwlilfdwlrq 5hylvlrqfrgh
docid027589 rev 4 213/228 stm32f756xx package information 227 6.6 lqfp208, 28 x 28 mm lo w-profile quad flat package information figure 94. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package outline 1. drawing is not to scale. table 119. lqfp208, 28 x 28 mm, 208- pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 -- - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 ' ' ' ( ( ( h / *$8*(3/$1( pp e & 6($7,1* 3/$1( fff & ,'(17,),&$7,21 3,1 f / $ $ $ $ 6)@.&@7 .
package information stm32f756xx 214/228 docid027589 rev 4 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 29.800 30.000 30.200 1. 1732 1.1811 1.1890 d1 27.800 28.000 28.200 1. 0945 1.1024 1.1102 d3 - 25.500 - - 1.0039 - e 29.800 30.000 30.200 1. 1732 1.1811 1.1890 e1 27.800 28.000 28.200 1. 0945 1.1024 1.1102 e3 - 25.500 - - 1.0039 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0 3.5 7.0 0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 119. lqfp208, 28 x 28 mm, 208- pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max
docid027589 rev 4 215/228 stm32f756xx package information 227 figure 95. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. -36
package information stm32f756xx 216/228 docid027589 rev 4 marking of engineering samples the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 96. lqfp208, 28 x 28 mm, 208-pin low-profile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 :: < 3lq lghqwlilhu 670)%*7 'dwhfrgh \hduzhhn 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 5
docid027589 rev 4 217/228 stm32f756xx package information 227 6.7 ufbga 176+25, 10 x 10 x 0.65 mm ultra thin-pitch ball grid array package information figure 97. ufbga 176+25, 10 10 0.65 mm ultra thin fine-pitch ball grid array package outline 1. drawing is not to scale. table 120. ufbga 176+25, 10 10 0.65 mm ultra thin fine-pitch ball grid array package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.050 0.080 0.110 0.002 0.0031 0.0043 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 d 9.950 10.000 10.050 0.3917 0.3937 0.3957 e 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - f 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 zdzs ^?]vp?ov ? & & z ? kddkds/t dkws/t ?eedoov $ hhh ? 0 iii ? 0 & & $ & $edoo lghqwlilhu $edoo lqgh[ duhd e
package information stm32f756xx 218/228 docid027589 rev 4 figure 98. ufbga176+25, 10 x 10 x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint table 121. ufbga176+25 recommended pcb design rules (0.65 mm pitch bga) dimension recommended values pitch 0.65 mm dpad 0.300 mm dsm 0.400 mm typ. (depends on the soldermask reg- istration tolerance) stencil opening 0.300 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.100 mm z&wzs 'sdg 'vp
docid027589 rev 4 219/228 stm32f756xx package information 227 marking of engineering samples the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 99. ufbga 176+25, 10 10 0.6 mm ultra thin fine-pitch ball grid array package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 5hylvlrqfrgh 670) 3urgxfwlghqwlilfdwlrq 'dwhfrgh <:: %doo$ lqghqwlilhu ,*. 5
package information stm32f756xx 220/228 docid027589 rev 4 6.8 tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package information figure 100. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package outline 1. drawing is not to scale. table 122. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.100 - - 0.0433 a1 0.150 - - 0.0059 - - a2 - 0.760 - - 0.0299 - b 0.350 0.400 0.450 0.0138 0.0157 0.0177 d 12.850 13.000 13.150 0.5118 0.5118 0.5177 d1 - 11.200 - - 0.4409 - e 12.850 13.000 13.150 0.5118 0.5118 0.5177 e1 - 11.200 - - 0.4409 - e - 0.800 - - 0.0315 - f - 0.900 - - 0.0354 - $/b0(b9 6hdwlqjsodqh $ h ) * ' 5 ?eedoov $ ( 7239,(: %277209,(: h $ $ < ; = ggg = ' ( hhh = < ; iii ? ? 0 0 = $edoo lghqwlilhu $edoo lqgh[duhd
docid027589 rev 4 221/228 stm32f756xx package information 227 figure 101. tfbga216, 13 x 13 x 0.8 mm thin fine-pitch ball grid array package recommended footprint g - 0.900 - - 0.0354 - ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 123. tfbga216 recommended pcb design rules (0.8 mm pitch bga) dimension recommended values pitch 0.8 dpad 0.400 mm dsm 0.470 mm typ. (depends on the soldermask reg- istration tolerance) stencil opening 0.400 mm stencil thickness between 0.100 mm and 0.125 mm pad trace width 0.120 mm table 122. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max $/b)3b9 'sdg 'vp
package information stm32f756xx 222/228 docid027589 rev 4 marking of engineering samples the following figure gives an example of topside marking orientation versus ball a1 identifier location. figure 102. tfbga216, 13 13 0.8 mm thin fine-pitch ball grid array package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 069 %doo$ lghqwlilhu 'dwhfrgh :88 5hylvlrqfrgh 3urgxfwlghqwlilfdwlrq 45.' /() 3
docid027589 rev 4 223/228 stm32f756xx package information 227 6.9 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 124. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 43 c/w thermal resistance junction-ambient tfbga100 - 8 8 mm / 0.8 mm pitch 57 thermal resistance junction-ambient wlcsp143 31.2 thermal resistance junction-ambient lqfp144 - 20 20 mm / 0.5 mm pitch 40 thermal resistance junction-ambient lqfp176 - 24 24 mm / 0.5 mm pitch 38 thermal resistance junction-ambient lqfp208 - 28 28 mm / 0.5 mm pitch 19 thermal resistance junction-ambient ufbga176 - 10 10 mm / 0.5 mm pitch 39 thermal resistance junction-ambient tfbga216 - 13 13 mm / 0.8 mm pitch 29
part numbering stm32f756xx 224/228 docid027589 rev 4 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 125. ordering information scheme example: stm32 f 756 v g t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 756= stm32f756xx, usb otg fs/hs, camera interface, ethernet, lcd- tft, cryptographic acceleration pin count v = 100 pins z = 143 and 144 pins i = 176 pins b = 208 pins n = 216 pins flash memory size e = 512 kbytes of flash memory g = 1024 kbytes of flash memory package t = lqfp k = ufbga h = tfbga y = wlcsp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and reel
docid027589 rev 4 225/228 stm32f756xx recommendations when using internal reset off 227 appendix a recommendations wh en using internal reset off when the internal reset is off, the following integrated features are no longer supported: ? the integrated power-on reset (por) / power-down reset (pdr) circuitry is disabled. ? the brownout reset (bor) circuitry must be disabled. ? the embedded programmable voltage detector (pvd) is disabled. ? v bat functionality is no more available and vbat pin should be connected to v dd . ? the over-drive mode is not supported. a.1 operating conditions table 126. limitations depending on the operating power supply range operating power supply range adc operation maximum flash memory access frequency with no wait states (f flashmax ) maximum flash memory access frequency with wait states (1)(2) 1. applicable only when the code is executed from flash memory. wh en the code is executed from ram, no wait state is required. 2. thanks to the art accelerator on itcm interface and l1-cache on axi interface, the number of wait states given here does not impact the execution speed from the flash memory since the art accelerator or l1- cache allows to achieve a performance equiva lent to 0-wait state program execution. i/o operation possible flash memory operations v dd =1.7 to 2.1 v (3) 3. v dd /v dda minimum value of 1.7 v, with the use of an external power supply supervisor (refer to section 2.17.1: internal reset on ). conversion time up to 1.2 msps 20 mhz 180 mhz with 8 wait states and over-drive off ? no i/o compensation 8-bit erase and program operations only
revision history stm32f756xx 226/228 docid027589 rev 4 revision history table 127. document revision history date revision changes 26-may-2015 1 initial release. 20-oct-2015 2 updated table 53: esd absolute maximum ratings adding packages. updated note of table 32: typical and maximum current consumptions in standby mode . updated figure 11: stm32f756vx lqfp100 pinout replacing pb13 and pb14 by pe13 and pe14. updated table 51: ems characteristics replacing 168 mhz by 216 mhz. updated section 2.9: quad-spi memory interface (quadspi) removing ?stm32f75xx?. removed table 86. ethernet dc electrical characteristics. updated all the notes removing ?not tested in production?. updated table 43: main pll characteristics , table 44: plli2s characteristics and table 45: pllisai characteristics fvco_out output at min value ?100? and vco freq at 100 mhz. updated table 13: stm32f756xx register boundary addresses replacing cortex-m4 by cortex-m7. updated table 87: dynamics characteristics: ethernet mac signals for mii td (txen) and td (txd) min value at 6.5 ns.
docid027589 rev 4 227/228 stm32f756xx revision history 227 10-dec-2015 3 updated table 10: stm32f756xx pin and ball definition additional function column: wkup1, 2, 3, 4, 5, 6 must be respectively pa0, pa2, pc1, pc13, pi8, pi11. updated table 62: adc characteristics adding v ref- negative voltage reference. update table 14: voltage characteristics adding table note 3. updated table 69: temperature s ensor calibration values memory addresses. updated table 72: internal reference voltage calibration values memory addresses. 16-feb-2016 4 updated table 52: emi characteristics modifying 25/180 mhz by 25/200 mhz. updated figure 13: stm32f756zx wlcsp143 ballout . added tfbga100 8 x 8 mm package: ? updated cover page. ? updated section 1: description . ? updated table 2: stm32f756xx features and peripheral counts . ? updated table 4: regulator on/off and internal reset on/off availability . ? updated section 3: pinouts and pin description adding figure 12: stm32f756vx tfbga100 ballout and adding tfbga100 ball description in table 10: stm32f756xx pin and ball definition . ? updated table 17: general operating conditions . ? updated table 53: esd absolute maximum ratings . ? updated notes below figure 43 and figure 44 . ? updated section 6: package information adding section 6.2: tfbga100, 8 x 8 x 0.8 mm thin fi ne-pitch ball grid array package information and adding thermal resistance in table 124: package thermal characteristics . ? updated table 10: stm32f756xx pin and ball definition note 5. updated table 35: peripheral current consumption peripheral consumption on apb1 and apb2. updated figure 18: stm32f756nx tfbga216 ballout . table 127. document revision history (continued) date revision changes
stm32f756xx 228/228 docid027589 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STM32F756ZG

	To Download STM32F756ZG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .